Publications related to Cray-1

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

Edoardo Charbon, Claudio Bruschini, Andrei Ardelean, Paul Mos, Arin Can Ülkü, Michael Alan Wayne

In this article, we report on SwissSPAD3 (SS3), a 500 x 500 pixel single-photon avalanche diode (SPAD) array, fabricated in 0.18-mu m CMOS technology. In this sensor, we introduce a novel dual-gate architecture with two contiguous temporal windows, or gate ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

PaRiS: Causally Consistent Transactions with Non-blocking Reads and Partial Replication

Willy Zwaenepoel, Diego Didona, Kristina Spirovska

Geo-replicated data platforms are at the backbone of several large-scale online services. Transactional Causal Consistency (TCC) is an attractive consistency level for building such platforms. TCC avoids many anomalies of eventual consistency, eschews the ...

2019

PaRiS: Causally Consistent Transactions with Non-blocking Reads and Partial Replication

Willy Zwaenepoel, Diego Didona, Kristina Spirovska

Geo-replicated data platforms are the backbone of several large-scale online services. Transactional Causal Consistency (TCC) is an attractive consistency level for building such platforms. TCC avoids many anomalies of eventual consistency, eschews the syn ...

IEEE COMPUTER SOC2019

Causal Consistency and Latency Optimality: Friend or Foe? [Extended Version]

Rachid Guerraoui, Willy Zwaenepoel, Diego Didona, Junxiong Wang

Causal consistency is an attractive consistency model for geo-replicated data stores. It is provably the strongest model that tolerates network partitions. It avoids the long latencies associated with strong consistency, and, especially when using read-onl ...

2018

Causal Consistency and Latency Optimality: Friend or Foe?

Rachid Guerraoui, Willy Zwaenepoel, Diego Didona, Junxiong Wang

ASSOC COMPUTING MACHINERY2018

Simulation, Analysis, and Verification of Substrate Currents for Layout Optimization of Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

Today circuit failures in Smart Power ICs due to substrate couplings are partially addressed during the circuit design phase. The state-of-the-art guidelines for the optimization of parasitic couplings provide mainly qualitative rules, which are difficult ...

Institute of Electrical and Electronics Engineers2016

3D-ICE: a Compact Thermal Model for Early-Stage Design of Liquid-Cooled ICs

David Atienza Alonso, Arvind Raj Mahankali Sridhar, Alessandro Vincenzi

Liquid-cooling using microchannel heat sinks etched on silicon dies is seen as a promising solution to the rising heat fluxes in two-dimensional and stacked three-dimensional integrated circuits. Development of such devices requires accurate and fast therm ...

Institute of Electrical and Electronics Engineers2014

A semi-analytical approach for optimized design of microchannel liquid-cooled ICs

David Atienza Alonso, Arvind Raj Mahankali Sridhar

The development of embedded and interlayer liquid cooling in integrated circuits (ICs) using silicon microchannels has gained interest in the recent years owing to the rise of on-chip heat uses that aggravate thermal reliability issues of the emerging 3D s ...

IEEE Press2014

A Semi-Analytical Thermal Modeling Framework for Liquid-Cooled ICs

David Atienza Alonso, Arvind Raj Mahankali Sridhar, Mohamed Mostafa Sabry Aly

While possessing the potential to replace conventional air-cooled heat sinks, inter-tier microchannel liquid cooling of 3D ICs also creates the problem of increased thermal gradients from the fluid inlet to outlet ports [1, 2]. These cooling-induced therma ...

Institute of Electrical and Electronics Engineers2014

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Cray-1

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications

PaRiS: Causally Consistent Transactions with Non-blocking Reads and Partial Replication

PaRiS: Causally Consistent Transactions with Non-blocking Reads and Partial Replication

Causal Consistency and Latency Optimality: Friend or Foe? [Extended Version]

Causal Consistency and Latency Optimality: Friend or Foe?

A low-voltage CMOS-compatible time-domain photodetector, device & front end electronics

Simulation, Analysis, and Verification of Substrate Currents for Layout Optimization of Smart Power ICs

3D-ICE: a Compact Thermal Model for Early-Stage Design of Liquid-Cooled ICs

A semi-analytical approach for optimized design of microchannel liquid-cooled ICs

A Semi-Analytical Thermal Modeling Framework for Liquid-Cooled ICs

Graph Chatbot

Chat with Graph Search

PaRiS: Causally Consistent Transactions with Non-blocking Reads and Partial Replication

Simulation, Analysis, and Verification of Substrate Currents for Layout Optimization of Smart Power ICs

PaRiS: Causally Consistent Transactions with Non-blocking Reads and Partial Replication

A low-voltage CMOS-compatible time-domain photodetector, device & front end electronics

Causal Consistency and Latency Optimality: Friend or Foe? [Extended Version]

Causal Consistency and Latency Optimality: Friend or Foe?

3D-ICE: a Compact Thermal Model for Early-Stage Design of Liquid-Cooled ICs

A semi-analytical approach for optimized design of microchannel liquid-cooled ICs

A Semi-Analytical Thermal Modeling Framework for Liquid-Cooled ICs

A 500 x 500 Dual-Gate SPAD Imager With 100% Temporal Aperture and 1 ns Minimum Gate Length for FLIM and Phasor Imaging Applications