Concept

Multiplexer

Related publications (30)

Resource Sharing in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Axel Marmet

To achieve resource-efficient hardware designs, high-level synthesis (HLS) tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed in conjunction with operation scheduling to ensure th ...

New York2023

Resource Sharing in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Axel Marmet

To achieve resource-efficient hardware designs, HLS tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed together with operation scheduling to ensure the best possible unit usage at ...

IEEE2022

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing

Mirjana Stojilovic, Hossein Asadi, Zeinab Seifoori

Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the ...

2021

Swap and Rotate: Lightweight Linear Layers for SPN-based Blockciphers

Serge Vaudenay, Francesco Regazzoni, Subhadeep Banik, Muhammed Fatih Balli

In CHES 2017, Jean et al. presented a paper on "Bit-Sliding" in which the authors proposed lightweight constructions for SPN based block ciphers like AES, PRESENT and SKINNY. The main idea behind these constructions was to reduce the length of the datapath ...

2020

Toward a Full-Flexible and Fast-Prototyping TOF-PET Block Detector Based on TDC-on-FPGA

Edoardo Charbon, Esteban Venialgo Araujo

Typically, a time-of-flight (TOF) positron emission tomography (PET) block detector is built using application-specific integrated circuits (ASICs), since they integrate a high number of channels at a reasonable power consumption and into a small area. How ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

A programmable low-power ADC interface for an ISFET sweat sensor used in a wearable multi-sensing system

Maher Kayal, Evgenia Voulgari, François Krummenacher

An application specific integrated circuit (ASIC) named ANTIGONE (ANalog To dIGital cONvErter) was designed in AMS 0.35 mu m technology to interface with four Ion-sensitive field-effect transistor (ISFET) sensors and perform real-time monitoring of some bi ...

IEEE2019

LUT-Based Hierarchical Reversible Logic Synthesis

Giovanni De Micheli, Mathias Soeken

We present a synthesis framework to map logic networks into quantum circuits for quantum computing. The synthesis framework is based on lookup-table (urn networks, which play a key role in conventional logic synthesis. Establishing a connection between LUT ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2019

Optimization Opportunities in RRAM-based FPGA Architectures

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang

Static Random Access Memory (SRAM)-based routing multiplexers, whatever structure is employed, share a common limitation: their area, delay and power increase linearly with the input size. This property results in most SRAM-based FPGA architectures ...

IEEE2017

Physical Design Considerations of One-level RRAM-based Routing Multiplexers

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang, Edouard Giacomin

Resistive Random Access Memory (RRAM) technology opens the opportunity for granting both high-performance and low- power features to routing multiplexers. In this paper, we study the physical design considerations related to RRAM- based routing mult ...

ACM2017

Pattern-based fpga logic block and clustering algorithm

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Xifan Tang

A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of inputs of a LUT, and LUTs in the group are indexed from 1 t ...

2016

Graph Chatbot

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.