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Related publications (28)

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by re ...

ASSOC COMPUTING MACHINERY2022

Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs

Paolo Ienne, Mikhail Asiatici

FPGAs rely on massive datapath parallelism to accelerate applications even with a low clock frequency. However, applications such as sparse linear algebra and graph analytics have their throughput limited by irregular accesses to external memory for which ...

ASSOC COMPUTING MACHINERY2019

Closing the Performance Gap Between Volatile and Persistent Key-Value Stores Using Cross-Referencing Logs

Matej Pavlovic

Key-Value (K-V) stores are an integral building block in modern datacenter applications. With byteaddressable persistent memory (PM) technologies, such as Intel/Micron's 3D XPoint, on the horizon, there has been an influx of new high performance K-V stores ...

USENIX ASSOC2018

Log-Free Concurrent Data Structures

Rachid Guerraoui, Aleksandar Dragojevic, Mihail Igor Zablotchi, Tudor Alexandru David

Non-volatile RAM (NVRAM) makes it possible for data structures to tolerate transient failures, assuming however that programmers have designed these structures such that their consistency is preserved upon recovery. Previous ap- proaches are typically tran ...

USENIX Association2018

Log-Free Concurrent Data Structures

Rachid Guerraoui, Aleksandar Dragojevic, Mihail Igor Zablotchi, Tudor Alexandru David

USENIX ASSOC2018

Elastic transactions

Rachid Guerraoui, Vincent Gramoli, Pascal Felber

This paper presents elastic transactions, an appealing alternative to traditional transactions, in particular to implement search structures in shared memory multicore architectures. Upon conflict detection, an elastic transaction might drop what it did so ...

Academic Press Inc Elsevier Science2017

Rake, Peel, Sketch

Robin Scheibler

The prototypical signal processing pipeline can be divided into four blocks. Representation of the signal in a basis suitable for processing. Enhancement of the meaningful part of the signal and noise reduction. Estimation of important statistical properti ...

EPFL2017

Hardware Attacks against Hash-based Cryptographic Algorithms

Aymeric Genet

This thesis surveys the current state of the art of hash-based cryptography with a view to finding vulnerabilities related to side-channel attacks and fault attacks. For side-channel investigation, we analyzed the power consumption of an Arduino Due microc ...

2017

Optimistic Concurrency with OPTIK

Rachid Guerraoui, Vasileios Trigonakis

We introduce OPTIK, a new practical design pattern for designing and implementing fast and scalable concurrent data structures. OPTIK relies on the commonly-used technique of version numbers for detecting conflicting concurrent operations. We show how to i ...

ACM Press2016

Towards Scalable Synchronization on Multi-Cores

Vasileios Trigonakis

The shift of commodity hardware from single- to multi-core processors in the early 2000s compelled software developers to take advantage of the available parallelism of multi-cores. Unfortunately, only few---so-called embarrassingly parallel---applications ...

EPFL2016

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