Publications related to Resistor–transistor logic

Monolithic Integration of GaN-Based NMOS Digital Logic Gate Circuits with E-Mode Power GaN MOSHEMTs

In this work, we demonstrate high-performance NMOS GaN-based logic gates including NOT, NAND, and NOR by integration of E/D-mode GaN MOSHEMTs on silicon substrates. The load-to-driver resistance ratio was optimized in these logic gates by using a multi-fin ...

IEEE2018

The Cryogenic Temperature Behavior of Bipolar, MOS, and DTMOS Transistors in Standard CMOS

Edoardo Charbon, Harald Arjan Robert Homulle, Fabio Sebastiano

Both CMOS bandgap voltage references and temperature sensors rely on the temperature behavior of either CMOS substrate BJTs or MOS transistors in weak inversion. Bipolar transistors are generally preferred over MOS transistors because of their lower spread ...

2018

Characterization of bipolar transistors for cryogenic temperature sensors in standard CMOS, 2016 IEEE SENSORS

Edoardo Charbon, Harald Arjan Robert Homulle, Fabio Sebastiano

This paper presents the cryogenic characterization of the bipolar substrate PNPs that are typically employed as sensing elements in CMOS integrated temperature sensors. PNPs realized in a standard 160-nm CMOS technology were characterized over the temperat ...

2017

Variability of Low Frequency Noise and mismatch in enclosed-gate and standard nMOSFETs

Matthias Bucher, Mathieu Yves Hervé Coustans

Variability of Low Frequency Noise (LFN) and Random Telegraph Noise (RTN) is an important concern for many analog CMOS integrated circuits. In this paper, transistors with enclosed gate layout are examined and compared with standard layout transistors, wit ...

IEEE2017

Method for speeding up boolean satisfiability

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù

A method for transforming a tautology check of an original logic circuit into a contradiction check of the original logic circuit and vice versa comprises interpreting the original logic circuit in terms of AND, OR, MAJ, MIN, XOR, XNOR, INV original logic ...

2016

Avalanche Microwave Noise Sources in Commercial 90-nm CMOS Technology

Christian Enz, Pierre-André Farine, Cyril Botteron, Gabriele Tasselli

This paper presents a microwave noise source implemented in a commercial CMOS technology. The circuit is based on the avalanche noise generated by both the source-to-bulk and the drain-to-bulk junctions in reverse breakdown. Two sources of different juncti ...

Institute of Electrical and Electronics Engineers2016

Underlap counterdoping as an efficient means to suppress lateral leakage in the electron–hole bilayer tunnel FET

Mihai Adrian Ionescu, Cem Alper, José Luis Padilla de la Torre, Pierpaolo Palestri

The electron-hole bilayer tunnel (EHBTFET). has been proposed as a density of states (DOS) switch capable of achieving a subthreshold slope lower than 60mV/decade at room temperature; however, one of the main challenges is the control of the lateral band-t ...

Institute of Physics2016

Double-Gate Negative-Capacitance MOSFET with PZT gate stack on Ultra-Thin Body SOI: an Experimentally Calibrated Simulation Study of Device Performance

Mihai Adrian Ionescu, Igor Stolichnov, Farzan Jazaeri, Ali Saeidi

In this work, we propose and investigate the high performance and low power design space of non-hysteretic negative capacitance MOSFETs for the 14nm node based on the calibrated simulations using an experimental gate stack with PZT ferroelectric to obtain ...

2016

Analysis of Substrate Currents Propagation in HVCMOS technology

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

This work reports the results of a layout-aware substrate modeling methodology for HVCMOS technologies. The model relies on the extraction of parasitic substrate network to simulate with circuit software parasitic lateral NPN bipolar transistors with multi ...

IEEE2016

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Resistor–transistor logic

Monolithic Integration of GaN-Based NMOS Digital Logic Gate Circuits with E-Mode Power GaN MOSHEMTs

The Cryogenic Temperature Behavior of Bipolar, MOS, and DTMOS Transistors in Standard CMOS

Characterization of bipolar transistors for cryogenic temperature sensors in standard CMOS, 2016 IEEE SENSORS

Variability of Low Frequency Noise and mismatch in enclosed-gate and standard nMOSFETs

Method for speeding up boolean satisfiability

Avalanche Microwave Noise Sources in Commercial 90-nm CMOS Technology

Underlap counterdoping as an efficient means to suppress lateral leakage in the electron–hole bilayer tunnel FET

Double-Gate Negative-Capacitance MOSFET with PZT gate stack on Ultra-Thin Body SOI: an Experimentally Calibrated Simulation Study of Device Performance

Analysis of Substrate Currents Propagation in HVCMOS technology

Practical Applications of Tunnel Field Effect Transistors

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Chat with Graph Search

Monolithic Integration of GaN-Based NMOS Digital Logic Gate Circuits with E-Mode Power GaN MOSHEMTs

Characterization of bipolar transistors for cryogenic temperature sensors in standard CMOS, 2016 IEEE SENSORS

The Cryogenic Temperature Behavior of Bipolar, MOS, and DTMOS Transistors in Standard CMOS

Variability of Low Frequency Noise and mismatch in enclosed-gate and standard nMOSFETs

Underlap counterdoping as an efficient means to suppress lateral leakage in the electron–hole bilayer tunnel FET

Avalanche Microwave Noise Sources in Commercial 90-nm CMOS Technology

Double-Gate Negative-Capacitance MOSFET with PZT gate stack on Ultra-Thin Body SOI: an Experimentally Calibrated Simulation Study of Device Performance

Analysis of Substrate Currents Propagation in HVCMOS technology

Method for speeding up boolean satisfiability

Practical Applications of Tunnel Field Effect Transistors