Publications related to Electronic system-level design and verification

Combining Dynamic & Static Scheduling in High-level Synthesis

A central task in high-level synthesis is scheduling: the allocation of operations to clock cycles. The classic approach to scheduling is static, in which each operation is mapped to a clock cycle at compile-time, but recent years have seen the emergence o ...

ASSOC COMPUTING MACHINERY2020

An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms

Marco Mattavelli, Simone Casale Brunet, Romuald Mosqueron, Endri Bezati

In recent years, the number and variety of heterogeneous multiprocessor system-on-chip MPSoCs, such as for instance Zynq platforms, has sensibly increased. However, today all design flow solutions capable of programming the different components of such pla ...

IEEE2019

Analysis, modeling and design of a CMOS Super-Regenerative Receiver for implanted medical devices under square and sinusoidal quench signals

Catherine Dehollain, Naci Pekçokgüler

Medical implant devices have found widespread application in recent years. The Super-Regenerative Receiver has been one preferred architecture due to its power advantage over other architectures. We present a detailed analysis of the circuits and their equ ...

ELSEVIER SCIENCE BV2019

Thin Hydrogel-Elastomer Multilayer Encapsulation for Soft Electronics

Stéphanie Lacour, Aaron Powers Gerratt, Jennifer Mary Adrienne Alice Macron

In the exciting race to design and engineer biointegrated and body-like electronic systems, many efforts concentrate on the integration of hydrogels in electronic assemblies. The versatility of hydrogels chemistry combined with their tissue-mimicking prope ...

WILEY2019

An FPGA-Based Test System for RRAM Technology Characterization

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Maxime Victor Thammasack, Armando Biscontini

Resistive random access memory (RRAM) technologies have recently gained large attention from the academic and industrial research communities. Significant efforts have been made to enhance the performance of the memory stacks from both communities through ...

2018

Design and Modelling of a Super-Regenerative Receiver for Medical Implant Devices

Catherine Dehollain, Naci Pekçokgüler

Medical implant devices have been widely used in recent years. The Super-Regenerative Receiver has been on preferred architecture due to its power advantage over other architectures. We present a detailed analysis of the circuits and their equivalent model ...

IEEE2018

Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

Christian Enz, Vincent Frédéric Camus, Alessandro Pezzotta, Jérémy Lucien Maurice Schlachter, Mattia Cacciotti

In this paper, the hardware acceleration of a tone-mapping algorithm for High-Dynamic-Range image processing is presented. Starting from the C++ source code, High-Level Synthesis has been performed using Xilinx SDSoC for a Xilinx Zynq SoC device. After an ...

IEEE2018

Portable Memristive Biosensing System as Effective Point-of-Care Device for Cancer Diagnostics

Giovanni De Micheli, Sandro Carrara, Danilo Demarchi, Ioulia Tzouvadaki, Abuduwaili Tuoheti

Memristive biosensors have been proved as excellent candidates for ultrasensitive biosensing. In this work, a novel portable bio-detection system based on memristive biosensors is designed, developed and tested for providing a significantly fast, automatic ...

IEEE2018

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Electronic system-level design and verification

Combining Dynamic & Static Scheduling in High-level Synthesis

SAT-Based Exact Synthesis for Multi-Level Logic Networks

An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms

An Input–Output Parametrization of Stabilizing Controllers: Amidst Youla and System Level Synthesis

Analysis, modeling and design of a CMOS Super-Regenerative Receiver for implanted medical devices under square and sinusoidal quench signals

Thin Hydrogel-Elastomer Multilayer Encapsulation for Soft Electronics

An FPGA-Based Test System for RRAM Technology Characterization

Design and Modelling of a Super-Regenerative Receiver for Medical Implant Devices

Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

Portable Memristive Biosensing System as Effective Point-of-Care Device for Cancer Diagnostics

Graph Chatbot

Chat with Graph Search

Hardware Acceleration of HDR-Image Tone Mapping on an FPGA-CPU Platform Through High-Level Synthesis

Portable Memristive Biosensing System as Effective Point-of-Care Device for Cancer Diagnostics

An Input–Output Parametrization of Stabilizing Controllers: Amidst Youla and System Level Synthesis

Analysis, modeling and design of a CMOS Super-Regenerative Receiver for implanted medical devices under square and sinusoidal quench signals

Combining Dynamic & Static Scheduling in High-level Synthesis

An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms

Thin Hydrogel-Elastomer Multilayer Encapsulation for Soft Electronics

An FPGA-Based Test System for RRAM Technology Characterization

Design and Modelling of a Super-Regenerative Receiver for Medical Implant Devices

SAT-Based Exact Synthesis for Multi-Level Logic Networks