Concept
Electronic system-level design and verification
Related publications (144)
Graph generative deep learning models with an application to circuit topologies
Modern integrated circuits are tiny yet incredibly complex technological artifacts, composed of millions and billions of individual structures working in unison.Managing their complexity and facilitating their design drove part of the co-evolution of moder ...
EPFL2024Highly Parallel RTL Simulation
Verification and testing of hardware heavily relies on cycle-accurate simulation of RTL.As single-processor performance is growing only slowly, conventional, single-threaded RTL simulation is becoming impractical for increasingly complex chip designs and s ...
EPFL2024Resource Sharing in Dataflow Circuits
Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Axel Marmet
To achieve resource-efficient hardware designs, high-level synthesis (HLS) tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed in conjunction with operation scheduling to ensure th ...
New York2023Ultra-Low Power Short-Range 60-GHz FMCW Radar Front-End
The millimeter wave (mmWave) frequency band is becoming very interesting over the past years because it provides the opportunity to operate using large bandwidths which are not available at lower frequencies. This enables new communication standards suppor ...
EPFL2023Neural System Level Synthesis: Learning over All Stabilizing Policies for Nonlinear Systems
Giancarlo Ferrari Trecate, Luca Furieri, Clara Lucía Galimberti
We address the problem of designing stabilizing control policies for nonlinear systems in discrete-time, while minimizing an arbitrary cost function. When the system is linear and the cost is convex, the System Level Synthesis (SLS) approach offers an effe ...
IEEE2022Unleashing Parallelism in Elastic Circuits with Faster Token Delivery
Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Ayatallah Ahmed Gamal Kamal Elakhras
High-level synthesis (HLS) is the process of automatically generating circuits out of high-level language descriptions. Previous research has shown that dynamically scheduled HLS through elastic circuit generation is successful at exploiting parallelism in ...
IEEE COMPUTER SOC2022From C/C plus plus Code to High-Performance Dataflow Circuits
Paolo Ienne, Andrea Guerrieri, Lana Josipovic
High-level synthesis (HLS) tools typically generate statically scheduled datapaths. Static scheduling implies that the resulting circuits have a hard time exploiting parallelism in code with potential memory dependences, with control dependences, or where ...
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022