Time-Sensitive Networking

Summary

Time-Sensitive Networking (TSN) is a set of standards under development by the Time-Sensitive Networking task group of the IEEE 802.1 working group. The TSN task group was formed in November 2012 by renaming the existing Audio Video Bridging Task Group and continuing its work. The name changed as a result of the extension of the working area of the standardization group. The standards define mechanisms for the time-sensitive transmission of data over deterministic Ethernet networks. The majority of projects define extensions to the IEEE 802.1Q – Bridges and Bridged Networks, which describes virtual LANs and network switches. These extensions in particular address the transmission of very low transmission latency and high availability. Applications include converged networks with real-time audio/video streaming and real-time control streams which are used in automotive or industrial control facilities. Background Standard Information technology network equipment

Official source

https://en.wikipedia.org/wiki/Time-Sensitive_Networking

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Simulation of Instability in Time-Sensitive Networks with Regulators and Imperfect Clocks

Guillermo Aguirre Rodrigo

Regulators are used in time-sensitive networks in order to reshape traffic reducing the burstiness generated by the aggregation systems within the network. Regulators, in terms of the IEEE TSN group are defined as Asynchronous Traffic Shaping or what in the literature is known as interleaved regulators. These regulators are placed before a multiplexing stage, shaping the outgoing traffic and cancelling the increased burstiness, allowing calculations of the worst-case delay to be performed. One of the main properties studied for regulators implies that they do not increase the worst-case delay in the network. So far, all the studies were performed assuming ideal clocks within the network. However, a recently published paper underlines the importance of taking into account non-ideal clocks while studying interleaved regulators properties, providing a theoretical proof that under certain circumstances, interleaved regulators can lead to system instability due to the unbounded delay through them. This thesis intends to continue with this study, providing a simulation proof that shows instability when interleaved regulators are simulated assuming non-ideal clocks. This is carried out in the network simulator ns-3. Along with the different developed modules, two are highlighted: local time and ATS modules. The former introduces the notion of local times in ns-3, whereas the latter implements regulators functionality in ns-3, following the implementation proposed by the IEEE TSN.

2020

Analysis of Dampers in Time-Sensitive Networks With Non-Ideal Clocks

Jean-Yves Le Boudec, Ehsan Mohammadpour

Dampers are devices that reduce delay jitter in the context of time-sensitive networks, by delaying packets for the amount written in packet headers. Jitter reduction is required by some real-time applications; beyond this, dampers have the potential to solve the burstiness cascade problem of deterministic networks in a scalable way, as they can be stateless. Dampers exist in several variants: some apply only to earliest-deadline-first schedulers, whereas others can be associated with any packet schedulers; some enforce FIFO ordering whereas some others do not. Existing analyses of dampers are specific to some implementations and some network configurations; also, they assume ideal, non-realistic clocks. In this paper, we provide a taxonomy of all existing dampers in general network settings and analyze their timing properties in presence of non-ideal clocks. In particular, we give formulas for computing residual jitter bounds of networks with dampers of any kind. We show that non-FIFO dampers may cause reordering due to clock non-idealities and that the combination of FIFO dampers with non-FIFO network elements may very negatively affect the performance bounds. Our results can be used to analyze timing properties and burstiness increase in any time-sensitive network, as we illustrate on an industrial case-study.

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2022

For time-sensitive networks, as in the context of IEEE TSN and IETF Detnet, cyclic dependencies are associated with certain fundamental properties such as improving availability and decreasing reconfiguration effort. Nevertheless, the existence of cyclic dependencies can cause very large latency bounds or even global instability, thus making the proof of the timing predictability of such networks a much more challenging issue. Cyclic dependencies can be removed by reshaping flows inside the network, by means of regulators. We consider FIFO-per-class networks with two types of regulators: per-flow regulators and interleaved regulators (the latter reshape entire flow aggregates). Such regulators come with a hardware cost that is less for an interleaved regulator than for a per-flow regulator; both can affect the latency bounds in different ways. We analyze the benefits of both types of regulators in partial and full deployments in terms of latency. First, we propose Low-Cost Acyclic Network (LCAN), a new algorithm for finding the optimum number of regulators for breaking all cyclic dependencies. Then, we provide another algorithm, Fixed-Point Total Flow Analysis (FP-TFA), for computing end-to-end delay bounds for general topologies, i.e., with and without cyclic dependencies. An extensive analysis of these proposed algorithms was conducted on generic grid topologies. For these test networks, we find that FP-TFA computes small latency bounds; but, at a medium to high utilization, the benefit of regulators becomes apparent. At high utilization or for high line transmission-rates, a small number of per-flow regulators has an effect on the latency bound larger than a small number of interleaved regulators. Moreover, interleaved regulators need to be placed everywhere in the network to provide noticeable improvements. We validate the applicability of our approaches on a realistic industrial time-sensitive network.

IEEE2019