Concept

Zen (microarchitecture)

Related publications (6)

System-Level Exploration of In-Package Wireless Communication for Multi-Chiplet Platforms

David Atienza Alonso, Marina Zapater Sancho, Giovanni Ansaloni, Rafael Medina Morillas, Joshua Alexander Harrison Klein

Multi-Chiplet architectures are being increasingly adopted to support the design of very large systems in a single package, facilitating the integration of heterogeneous components and improving manufacturing yield. However, chiplet-based solutions have to ...

2023

Quantum information density scaling and qubit operation time constraints of CMOS silicon-based quantum computer architectures

Edoardo Charbon, Fabio Sebastiano

Even the quantum simulation of an apparently simple molecule such as Fe2S2 requires a considerable number of qubits of the order of 106, while more complex molecules such as alanine (C3H7NO2) require about a hundred times more. In order to assess such a mu ...

2017

Double-Gate Negative-Capacitance MOSFET with PZT gate stack on Ultra-Thin Body SOI: an Experimentally Calibrated Simulation Study of Device Performance

Mihai Adrian Ionescu, Igor Stolichnov, Farzan Jazaeri, Ali Saeidi

In this work, we propose and investigate the high performance and low power design space of non-hysteretic negative capacitance MOSFETs for the 14nm node based on the calibrated simulations using an experimental gate stack with PZT ferroelectric to obtain ...

2016

Die-Stacked DRAM Caches for Servers: Hit Ratio, Latency, or Bandwidth? Have It All with Footprint Cache

Babak Falsafi, Stavros Volos

Recent research advocates using large die-stacked DRAM caches to break the memory bandwidth wall. Existing DRAM cache designs fall into one of two categories — block-based and page-based. The former organize data in conventional blocks (e.g., 64B), ensurin ...

ACM2013

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The explosive growth in digital data and its growing role in real-time decision support motivate the design of high-performance database management systems (DBMSs). Meanwhile, slowdown in supply voltage scaling has stymied improvements in core performance ...

2013

For many years, lithographic resolution has been the main obstacle in keeping the pace of transistor densification to meet Moore's Law. For the 32 nm node and beyond, new lithography techniques will be used, including immersion ArF (iArF) lithography and e ...

International Society for Optics and Photonics2010

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