Publications related to Row hammer

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher pow ...

MDPI2024

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

Andreas Peter Burg, Robert Giterman, Halil Andac Yigit, Emmanuel Nieto Casarrubias

Gain-cell embedded DRAM (GC-eDRAM) is a high-density logic-compatible alternative to conventional static random-access memory (SRAM) and embedded DRAM (eDRAM). However, GC-eDRAM suffers from a reduced data retention time (DRT) at deeply-scaled process node ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

Quantum error correction using squeezed Schrodinger cat states

Vincenzo Savona, Fabrizio Minganti, David Schlegel

Bosonic quantum codes redundantly encode quantum information in the states of a quantum harmonic oscillator, making it possible to detect and correct errors. Schrodinger cat codes-based on the superposition of two coherent states with opposite displacement ...

AMER PHYSICAL SOC2022

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Robert Giterman, Odem Harel

Embedded memories, mostly implemented with static random access memory (SRAM), dominate the area and power of integrated circuits. Gain-cell embedded DRAM (GC-eDRAM) is an alternative to SRAM due to its high density, low power consumption, and two-ported f ...

ELSEVIER SCI LTD2020

Bridging the Latency Gap between NVM and DRAM for Latency-bound Operations

Anastasia Ailamaki, Georgios Psaropoulos

Non-Volatile Memory (NVM) technologies exhibit 4× the read access latency of conventional DRAM. When the working set does not fit in the processor cache, this latency gap between DRAM and NVM leads to more than 2× runtime increase for queries dominated by ...

ACM2019

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Atri Bhattacharyya

When applications have unpredictable memory accesses or irregular control flow, dataflow circuits overcome the limitations of statically scheduled high-level synthesis (HLS). If memory dependences cannot be determined at compile time, dataflow circuits rel ...

IEEE COMPUTER SOC2019

MATHICSE Technical Report : Low-rank approximation in the Frobenius norm by column and row subset selection

Daniel Kressner, Alice Cortinovis

A CUR approximation of a matrix A is a particular type of low-rank approximation where C and R consist of columns and rows of A, respectively. One way to obtain such an approximation is to apply column subset selection to A and its transpose. In this work, ...

MATHICSE2019

Design Guidelines for High-Performance SCM Hierarchies

Babak Falsafi, Edouard Bugnion, Alexandros Daglis, Javier Picorel Obando, Mark Johnathon Sutherland, Dionysios Pnevmatikatos, Dmitrii Ustiugov

With emerging storage-class memory (SCM) nearing commercialization, there is evidence that it will deliver the much-anticipated high density and access latencies within only a fewfactors of DRAM. Nevertheless, the latency-sensitive nature of memory-residen ...

ACM2018

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Row hammer

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

Quantum error correction using squeezed Schrodinger cat states

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Bridging the Latency Gap between NVM and DRAM for Latency-bound Operations

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

MATHICSE Technical Report : Low-rank approximation in the Frobenius norm by column and row subset selection

Design Guidelines for High-Performance SCM Hierarchies

Graph Chatbot

Chat with Graph Search

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

Quantum error correction using squeezed Schrodinger cat states

Bridging the Latency Gap between NVM and DRAM for Latency-bound Operations

MATHICSE Technical Report : Low-rank approximation in the Frobenius norm by column and row subset selection

Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs

Design Guidelines for High-Performance SCM Hierarchies

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs