Concept

Address space

Related publications (67)

Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads

David Atienza Alonso, Marina Zapater Sancho, Luis Maria Costero Valero, Darong Huang, Qunyou Liu

The increasing demand for computing power and the emergence of heterogeneous computing architectures have driven the exploration of innovative techniques to address current limitations in both the compute and memory subsystems. One such solution is the use ...

2024

Secure Interface Design Leveraging Hardware/Software Support

Atri Bhattacharyya

Computer systems rely heavily on abstraction to manage the exponential growth of complexity across hardware and software. Due to practical considerations of compatibility between components of these complex systems across generations, developers have favou ...

EPFL2024

Rebooting Virtual Memory with Midgard

Siddharth Gupta

Virtual Memory (VM) is a critical programming abstraction that is widely used in various modern computing platforms. With the rise of datacenter computing and birth of planet-scale online services, the semantic and capacity requirements from memory have ev ...

EPFL2023

Entrepreneurial Opportunities and Threats in the Era of Grand Societal Challenges

Enrico Bergamini

We live in an era defined by attempts to grapple with an ever-expanding array of grand societal challenges (GCs). These challenges comprise transformational social and environmental issues, such as environmental degradation and global pandemics, and the cr ...

EPFL2023

Advances in polymer-based nanocomposite membranes for water remediation: Preparation methods, critical issues and mechanisms

Sami Rtimi

Membrane technology is a growing tool for contaminants removal from polluted water. Although various types of polymeric membranes have been developed for water remediation, the common drawbacks like fouling, hydrophobicity and low mechanical strength are y ...

London2023

Method for reading and writing unreliable memories and a corresponding memory controller device and memory

Andreas Peter Burg, Reza Ghanaatian Jahromi

A method of accessing a memory space of a memory device with a decoder, the memory space having faults, including the steps of performing a memory access operation by an electronic device to a access a logical memory space of the memory device, and randomi ...

2022

A Canvas for the Ethical Design of Learning Experiences with Digital Tools

Denis Gillet, Patrick Jermann, Roland John Tormey, Cécile Hardebolle, Adrian Christian Holzer, Pascal Felber

The use of digital tools has drastically increased in engineering education, accelerated by the COVID-19 pandemic. These tools generate important ethical issues, in particular in terms of privacy and fairness. However, very few teacher training programmes ...

2022

Rebooting Virtual Memory with Midgard

Babak Falsafi, Mathias Josef Payer, Siddharth Gupta, Atri Bhattacharyya, Yunho Oh, Abhishek Bhattacharjee

Computer systems designers are building cache hierarchies with higher capacity to capture the ever-increasing working sets of modern workloads. Cache hierarchies with higher capacity improve system performance but shift the performance bottleneck to addres ...

2021

Reply to the Comment on "Phase transitions, screening and dielectric response of CsPbBr3" by S. Svirskas, S. Balciunas, M. Simenas, G. Usevicius, M. Kinka, M. Velicka, D. Kubicki, M. E. Castillo, A. Karabanov, V. V. Shvartsman, M. R. Soares, V. Sablinskas, A. N. Salak, D. C. Lupascu and J. Banys, J. Mater. Chem. A, 2020, 8, 14015

Dominik Józef Kubicki

In this reply, we address the concerns that were raised about our paper on CsPbBr3 single crystals. M. Szafranski criticized the dielectric and DSC data in our original paper claiming that they were affected by the experimental artefacts or poor quality of ...

ROYAL SOC CHEMISTRY2021

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

Babak Falsafi, Javier Picorel Obando, Abhishek Bhattacharjee

Virtual memory (VM) is critical to the usability and programmability of hardware accelerators. Unfortunately, implementing accelerator VM efficiently is challenging because the area and power constraints make it difficult to employ the large multi-level TL ...

2020

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