Publications related to Cache control instruction

Determining an optimum quantity of interleaved instruction streams of defined coroutines

Anastasia Ailamaki, Georgios Psaropoulos

A method for optimizing memory access for database operations is provided. The method may include performing a first database operation by at least executing a first instruction stream associated with the first database operation. The first database opera ...

2023

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

David Atienza Alonso, Giovanni Ansaloni, Alireza Amirshahi, Joshua Alexander Harrison Klein

Transformer models have achieved impressive results in various AI scenarios, ranging from vision to natural language processing. However, their computational complexity and their vast number of parameters hinder their implementations on resource-constraine ...

2023

HPCache: memory-efficient OLAP through proportional caching revisited

Anastasia Ailamaki, Periklis Chrysogelos, Hamish Mcniece Hill Nicholson

Analytical engines rely on in-memory data caching to avoid storage accesses and provide timely responses by keeping the most frequently accessed data in memory. Purely frequency- and time-based caching decisions, however, are a proxy of the expected query ...

New York2023

WR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

David Atienza Alonso, Miguel Peon Quiros, Benoît Walter Denkinger

Edge-computing requires high-performance energy-efficient embedded systems. Fixed-function or custom accelerators, such as FFT or FIR filter engines, are very efficient at implementing a particular functionality for a given set of constraints. However, the ...

2022

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Paolo Ienne, Mikhail Asiatici

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by re ...

ASSOC COMPUTING MACHINERY2022

Rebooting Virtual Memory with Midgard

Babak Falsafi, Mathias Josef Payer, Siddharth Gupta, Atri Bhattacharyya, Yunho Oh, Abhishek Bhattacharjee

Computer systems designers are building cache hierarchies with higher capacity to capture the ever-increasing working sets of modern workloads. Cache hierarchies with higher capacity improve system performance but shift the performance bottleneck to addres ...

2021

Micro-architectural analysis of in-memory OLTP: Revisited

Anastasia Ailamaki, Danica Porobic, Utku Sirin

Micro-architectural behavior of traditional disk-based online transaction processing (OLTP) systems has been investigated extensively over the past couple of decades. Results show that traditional OLTP systems mostly under-utilize the available micro-archi ...

2021

Performance Characterization of HTAP Workloads

Anastasia Ailamaki, Sandhya Dwarkadas, Utku Sirin

Hybrid Transactional and Analytical Processing (HTAP) systems have become popular in the past decade. HTAP systems allow running transactional and analytical processing workloads on the same data and hardware. As a result, they suffer from workload interfe ...

IEEE COMPUTER SOC2021

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Cache control instruction

Determining an optimum quantity of interleaved instruction streams of defined coroutines

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

Fast correlation function calculator A high-performance pair-counting toolkit

HPCache: memory-efficient OLAP through proportional caching revisited

WR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Columnar Storage Optimization and Caching for Data Lakes

Rebooting Virtual Memory with Midgard

Micro-architectural analysis of in-memory OLTP: Revisited

Performance Characterization of HTAP Workloads

Graph Chatbot

Chat with Graph Search

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

TiC-SAT: Tightly-coupled Systolic Accelerator for Transformers

Fast correlation function calculator A high-performance pair-counting toolkit

Determining an optimum quantity of interleaved instruction streams of defined coroutines

HPCache: memory-efficient OLAP through proportional caching revisited

WR2A: A Very-Wide-Register Reconfigurable-Array Architecture for Low-Power Embedded Devices

Micro-architectural analysis of in-memory OLTP: Revisited

Rebooting Virtual Memory with Midgard

Columnar Storage Optimization and Caching for Data Lakes

Performance Characterization of HTAP Workloads