Concept

Memory address

Related publications (129)

3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory

Giovanni De Micheli, Yusuf Leblebici, Luca Benini, Giulia Beanato

Shared L1 memories are of interest for tightly- coupled processor clusters in programmable accelerators as they provide a convenient shared memory abstraction while avoiding cache coherence overheads. The performance of a shared-L1 memory critically depend ...

2012

Path Processing using Solid State Storage

Manoussos Gavriil Athanassoulis

Recent advances in solid state technology have led to the introduction of Solid State Drives (SSDs). Todays SSDs store data persistently using NAND ﬂash memory. While SSDs are more expensive than hard disks when measured in dollars per gigabyte, they are s ...

2012

Scaladoc Diagrams for Class Hierarchies

Damien Obrist

On numerous occasions it has been pointed out that the class hierarchy of the Scala standard library is hard to follow. This project aims at addressing the problem by automatically generating interactive class hierarchy diagrams in the scaladoc tool. ...

2012

SLIC Superpixels Compared to State-of-the-art Superpixel Methods

Pascal Fua, Sabine Süsstrunk, Radhakrishna Achanta, Kevin Smith, Aurélien Lucchi, Appu Shaji

Computer vision applications have come to rely increasingly on superpixels in recent years, but it is not always clear what constitutes a good superpixel algorithm. In an effort to understand the benefits and drawbacks of existing methods, we empirically c ...

Institute of Electrical and Electronics Engineers2012

Methodology for Developing Real-time Motorway Traffic Risk Identification Models Using Individual Vehicle Data

André-Gilles Dumont, Edward Chung, Ashish Bhaskar, Minh Hai Pham

Most of existing motorway traffic safety studies using disaggregate traffic flow data aim at developing models for identifying real-time traffic risks by comparing pre-crash and non-crash conditions. One of serious shortcomings in those studies is that non ...

2011

Verification of STM on relaxed memory models

Rachid Guerraoui, Vasu Singh

Software transactional memories (STM) are described in the literature with assumptions of sequentially consistent program execution and atomicity of high level operations like read, write, and abort. However, in a realistic setting, processors use relaxed ...

Springer Verlag2011

A Novel Conflict-Free Memory and Processor Architecture for DVB-T2 LDPC Decoding

Alberto Jimenez Pacheco

In this paper, we present a flexible architecture for an LDPC decoder that fully exploits the structure of the codes defined in the DVB-T2 standard (Digital Video Broadcasting - Second Generation Terrestrial). We propose a processor and memory architecture ...

2011

On some numerical aspects of an active strain model in cardiac mechanics

Alfio Quarteroni, Ricardo Esteban Ruiz Baier, Simone Rossi

We are interested in the development, implementation and testing of an orthotropic model for cardiac contraction based on an active strain decomposition. Our model addresses the coupling of a transversely isotropic mechanical description at the cell level, ...

Wiley2011

A Federated Search and Social Recommendation Widget

Denis Gillet, Sten Govaerts

This paper presents a federated search and social recommen- dation widget. It describes the widget’s interface and the un- derlying social recommendation engine. A preliminary eval- uation of the widget’s usability and usefulness involving 15 subjects is a ...

2011

Memory Safety of Floating-Point Computations

Johannes Kinder

Concepts and technologies are described herein for determining memory safety of floating-point computations. The concepts and technologies described herein analyze code to determine if any floating-point computations exist in the code, and if so, if the fl ...

US Patent & Trademark Office2010

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