Publications related to Instruction unit

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

High-performance branch target buffers (BTBs) and the L1I cache are key to high-performance front-end. Modern branch predictors are highly accurate, but with an increase in code footprint in modern-day server workloads, BTB and L1I misses are still frequen ...

ASSOC COMPUTING MACHINERY2022

JPEG XS-A New Standard for Visually Lossless Low-Latency Lightweight Image Coding

Touradj Ebrahimi

Joint Photographic Experts Group (JPEG) XS is a new International Standard from the JPEG Committee (formally known as ISO/International Electrotechnical Commission (IEC) JTC1/SC29/WG1). It defines an interoperable, visually lossless low-latency lightweight ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2021

Biosensors for Bimolecular Computing: a Review and Future Perspectives

Sandro Carrara, Danilo Demarchi, Simone Aiassa

Biomolecular computing is the field of engineering where computation, storage, communication, and coding are obtained by exploiting interactions between biomolecules, especially DNA, RNA, and enzymes. They are a promising solution in a long-term vision, br ...

SPRINGER2020

Prefetched Address Translation

Edouard Bugnion, Boris Robert Grot, Dmitrii Ustiugov

With explosive growth in dataset sizes and increasing machine memory capacities, per-application memory footprints are commonly reaching into hundreds of GBs. Such huge datasets pressure the TLB, resulting in frequent misses that must be resolved through a ...

ASSOC COMPUTING MACHINERY2019

Design and optimization of a high-temperature latent heat storage unit

Sophia Haussener, Ehsan Rezaei, Alberto Ortona, Maurizio Barbato

High-temperature latent heat thermal energy storage systems offer compact storage solutions, benefiting from the large latent heat of phase change materials. Common challenges in their design process are the low thermal conductivity of the phase change mat ...

2019

Low-Overhead Dynamic Instruction Mix Generation using Hybrid Basic Block Profiling

Willy Zwaenepoel, Andrzej Pawel Nowak

Dynamic instruction mixes form an important part of the toolkits of performance tuners, compiler writers, and CPU architects. Instruction mixes are traditionally generated using software instrumentation, an accurate yet slow method, that is normally limite ...

2018

Unified prefetching into instruction cache and branch target buffer

Babak Falsafi, Boris Robert Grot, Ilknur Cansu Kaynak

A system and method of coupling a Branch Target Buffer (BTB) content of a BTB with an instruction cache content of an instruction cache. The method includes: tagging a plurality of target buffer entries that belong to branches within a same instruction blo ...

2017

STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

Anastasia Ailamaki, Pinar Tözün, Xin Tong

Online transaction processing (OLTP) workload performance suffers from instruction stalls; the instruction footprint of a typical transaction exceeds by far the capacity of an L1 cache, leading to ongoing cache thrashing. Several proposed techniques remove ...

2013

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Instruction unit

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

JPEG XS-A New Standard for Visually Lossless Low-Latency Lightweight Image Coding

Biosensors for Bimolecular Computing: a Review and Future Perspectives

Prefetched Address Translation

Design and optimization of a high-temperature latent heat storage unit

Low-Overhead Dynamic Instruction Mix Generation using Hybrid Basic Block Profiling

Optimized Memory Access For Dynamically Scheduled High Level Synthesis

Unified prefetching into instruction cache and branch target buffer

Memory Systems and Interconnects for Scale-Out Servers

STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

Graph Chatbot

Chat with Graph Search

Micro BTB: A High Performance and Storage Efficient Last-Level Branch Target Buffer for Servers

Low-Overhead Dynamic Instruction Mix Generation using Hybrid Basic Block Profiling

Memory Systems and Interconnects for Scale-Out Servers

Prefetched Address Translation

Design and optimization of a high-temperature latent heat storage unit

STREX: Boosting Instruction Cache Reuse in OLTP Workloads Through Stratified Transaction Execution

Biosensors for Bimolecular Computing: a Review and Future Perspectives

JPEG XS-A New Standard for Visually Lossless Low-Latency Lightweight Image Coding

Unified prefetching into instruction cache and branch target buffer

Optimized Memory Access For Dynamically Scheduled High Level Synthesis