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Gate array

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Active wire fences for multitenant FPGAs

Learning With Your PETS

Evaluating, Exploiting, and Hiding Power Side-Channel Leakage of Remote FPGAs

Automating the Design of Programmable Interconnect for Reconfigurable Architectures

Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs

IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck

A Visionary Look at the Security of Reconfigurable Cloud Computing

RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks

Hardware-Software Co-design for Improved Resource Utilization in DNN Accelerators

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI