Concept

Speaking clock

Related publications (26)

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Timing Uncertainty in 3-D Clock Trees due to Process Variations and Power Supply Noise

Giovanni De Micheli, Xifan Tang, Vasileios Pavlidis, Hu Xu, Wayne Burleson

Clock distribution networks are affected by different sources of variations. The resulting clock uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical model of skitter, which consists of clock skew and jitter ...

Institute of Electrical and Electronics Engineers2013

Three-dimensional (3-D) integration is a promising solution to further enhance the density and performance of modern integrated circuits (ICs). In 3-D ICs, multiple dies (tiers or planes) are vertically stacked. These dies can be designed and fabricated se ...

EPFL2012

A Low-Overhead Method for Pre-bond Test of Resonant 3-D Clock Distribution Networks

Giovanni De Micheli, Vasileios Pavlidis, Somayyeh Rahimian Omam

Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low power alternatives to con- ventional ...

2012

The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu, Wayne Burleson

In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock s ...

Ieee2012

Microwave cavities, or microwave resonators, are used in a variety of applications, including filters, oscillators, frequency meters, and tuned amplifiers. The ever-increasing demand for compact and/or portable telecommunication systems drives the need for ...

EPFL2012

Skew Variability in 3-D ICs with Multiple Clock Domains

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

The effect of process variations on the clock skew in three dimensional (3-D) circuits with multiple clock domains is investigated. In 3-D ICs, the combined effect of inter-die and intra-die process variations should be considered in the design of clock di ...

Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2011

Clock Distribution Networks in 3-D Integrated Systems

Vasileios Pavlidis

3-D integration is an important technology that addresses fundamental limitations in on-chip interconnects. Several design issues related to 3-D circuits, such as multiplane synchronization, however, need to be addressed. A comparison of three 3-D clock di ...

2011

Silicon Resonator Based 3.2 mu W Real Time Clock With +/- 10 ppm Frequency Accuracy

David Ruffieux, François Krummenacher, Aurélie Pezous

This paper presents an ultra-low power generic compensation scheme that is used to implement a real time clock based on an AlN-driven 1 MHz uncompensated silicon resonator achieving 3.2 mu W power dissipation at 1 V and +/- 10 ppm frequency accuracy over a ...

2010

A widely-tunable and power-scalable clock generator for ultra-low power (ULP) applications is presented. Benefitting from a novel self-adjustable loop frequency response, the proposed phase-locked loop based clock generator exhibits a tuning range of three ...

2010

Process-induced skew variation for scaled 2-D and 3-D ICs

Giovanni De Micheli, Vasileios Pavlidis, Hu Xu

Technology scaling and three-dimensional integration are two design paradigms that offer high device density. Process variations affect these design paradigms in different ways. The effect of process variations on clock skew for a 2-D circuit implemented a ...

ACM Press2010