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Concept
Sandy Bridge
Summary
Sandy Bridge is the codename for Intel's 32 nm microarchitecture used in the second generation of the Intel Core processors (Core i7, i5, i3). The Sandy Bridge microarchitecture is the successor to Nehalem and Westmere microarchitecture. Intel demonstrated a Sandy Bridge processor in 2009, and released first products based on the architecture in January 2011 under the Core brand.
Sandy Bridge is manufactured in the 32 nm process and has a soldered contact with the die and IHS (Integrated Heat Spreader), while Intel's subsequent generation Ivy Bridge uses a 22 nm die shrink and a TIM (Thermal Interface Material) between the die and the IHS.
Intel demonstrated a Sandy Bridge processor with A1 stepping at 2 GHz during the Intel Developer Forum in September 2009.
Upgraded features from Nehalem include:
Intel Turbo Boost 2.0
32 KB data + 32 KB instruction L1 cache and 256 KB L2 cache per core
Shared L3 cache which includes the processor graphics (LGA 1155)
64-byte cache line size
New μOP cache, up to 1536-entry
Improved 3 integer ALU, 2 vector ALU and 2 AGU per core
Two load/store operations per CPU cycle for each memory channel
Decoded micro-operation cache, and enlarged, optimized branch predictor
Sandy Bridge retains the four branch predictors found in Nehalem: the branch target buffer (BTB), indirect branch target array, loop detector and renamed return stack buffer (RSB). Sandy Bridge has a single BTB that holds twice as many branch targets as the L1 and L2 BTBs in Nehalem.
Improved performance for transcendental mathematics, AES encryption (AES instruction set), and SHA-1 hashing
256-bit/cycle ring bus interconnect between cores, graphics, cache and System Agent Domain
Advanced Vector Extensions (AVX) 256-bit instruction set with wider vectors, new extensible syntax and rich functionality
Up to 8 physical cores, or 16 logical cores through hyper-threading (From 6 core/12 thread)
Integration of the GMCH (integrated graphics and memory controller) and processor into a single die inside the processor package.
Official source
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