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Concept
Nehalem (microarchitecture)
Summary
Nehalem nəˈheɪləm is the codename for Intel's 45 nm microarchitecture released in November 2008. It was used in the first-generation of the Intel Core i5 and i7 processors, and succeeds the older Core microarchitecture used on Core 2 processors. The term "Nehalem" comes from the Nehalem River.
Nehalem is built on the 45 nm process, is able to run at higher clock speeds, and is more energy-efficient than Penryn microprocessors. Hyper-threading is reintroduced, along with a reduction in L2 cache size, as well as an enlarged L3 cache that is shared among all cores. Nehalem is an architecture that differs radically from NetBurst, while retaining some of the latter's minor features.
Nehalem later received a die-shrink to 32 nm with Westmere, and was fully succeeded by "second-generation" Sandy Bridge in January 2011.
Cache line block on L2/L3 cache was reduced from 128 bytes in NetBurst & Conroe/Penryn to 64 bytes per line in this generation (same size as Yonah and Pentium M).
Hyper-threading reintroduced.
Intel Turbo Boost 1.0.
2–24 MiB L3 cache
Instruction Fetch Unit (IFU) containing second-level branch predictor with two level Branch Target Buffer (BTB) and Return Stack Buffer (RSB). Nehalem also supports all predictor types previously used in Intel's processors like Indirect Predictor and Loop Detector.
sTLB (second level unified translation lookaside buffer) (i.e. both instructions and data) that contains 512 entries for small pages only, and is again 4 way associative.
3 integer ALU, 2 vector ALU and 2 AGU per core.
Native (all processor cores on a single die) quad- and octa-core processors
Intel QuickPath Interconnect in high-end models replacing the legacy front side bus
64 KB L1 cache per core (32 KB L1 data and 32 KB L1 instruction), and 256 KB L2 cache per core.
Integration of PCI Express and DMI into the processor in mid-range models, replacing the northbridge
Integrated memory controller supporting two or three memory channels of DDR3 SDRAM or four FB-DIMM2 channels
Second-generation Intel Virtualization Technology, which introduced Extended Page Table support, virtual processor identifiers (VPIDs), and non-maskable interrupt-window exiting
SSE4.
Official source
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