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Related publications (30)

Distributed Learning of CNNs on Heterogeneous CPU/GPU Architectures

José Pedro Rebelo Ferreira Marques, Gabriel Falcao Paiva Fernandes

The convolutional neural networks (CNNs) have proven to be powerful classification tools in tasks that range from check reading to medical diagnosis, reaching close to human perception, and in some cases surpassing it. However, the problems to solve are be ...

TAYLOR & FRANCIS INC2018

Copper TSV-Based Process Development for Die-Level Homogeneous and Heterogeneous 3D Integration Platform

Seniz Esra Küçük

Research and development efforts on chip and wafer-scale 3D integration for system miniaturization have been continuing for more than a decade. However, there are still only a handful of 3D integrated products available in the market due to the high cost a ...

EPFL2017

Analysis of CMS noise reduction for 65 nm CIS

Christian Enz, Assim Boukhayma, Raffaele Capoccia

This work explores the combination of a downscaled technology with in-pixel source-follower (SF) optimization, a high column-level gain and an analog implementation of Correlated-Multiple-Sampling (CMS) for noise reduction of CIS readout chains. Transient ...

2017

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

Andreas Peter Burg, Adam Shmuel Teman, Thomas Christoph Müller, Andrea Bonetti, Jeremy Hugues-Felix Constantin, Lorenz Flavio Schmid

This paper presents DynOR, a 32-bit 6-stage OpenRISC microprocessor with dynamic clock adjustment. To alleviate the issue of unused dynamic timing margins, the clock period of the processor is adjusted on a cycle-by-cycle level, based on the instruction ty ...

Ieee2016

Sub-electron CIS noise analysis in 65 nm process

Christian Enz, Assim Boukhayma, Raffaele Capoccia

For a 4T pixel-based CMOS image sensors (CIS) readout chain, with column-level amplification and CDS, we show that the input-referred total noise in a standard 65 nm process can be reduced to 0.37 e-rms. Based on transient noise simulation using Eldo, the ...

2016

Stabilization of electrodynamic bearings with active magnetic dampers

Qingwen Cui

Electrodynamic Bearings (EDBs) are a kind of passive magnetic bearings that exploits the interaction between the induced eddy currents in a conductor and a magnetic field to provide re-storing forces. They have been regarded as an appealing alternative to ...

EPFL2016

Characterization of the Impact of Hardware Islands on OLTP

Anastasia Ailamaki, Miguel Sérgio De Oliveira Branco, Pinar Tözün, Ippokratis Pandis, Danica Porobic

Modern hardware is abundantly parallel and increasingly heterogeneous. The numerous processing cores have non-uniform access latencies to the main memory and processor caches, which causes variability in the communication costs. Unfortunately, database sys ...

Springer Verlag2016

GPU Acceleration for Simulating Massively Parallel Many-Core Platforms

David Atienza Alonso, Luca Benini, Martino Ruggiero, Shivani Raghav

Emerging massively parallel architectures such as a general-purpose processor plus many-core programmable accelerators are creating an increasing demand for novel methods to perform their architectural simulation. Most state-of-the-art simulation technolog ...

Institute of Electrical and Electronics Engineers2015

Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing

David Atienza Alonso, Andreas Peter Burg, Jeremy Hugues-Felix Constantin, Ahmed Yasir Dogan

A multi-core architecture with ultra-low power consumption is needed for a wide variety of applications, especially in the bio-medical domain. In this patent, an ultra-low power multi-core architecture is presented: it is composed of one or more cores, sev ...

2014

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

Georgios Karakonstantis

In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped p ...

Elsevier2014

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