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This paper will introduce new modeling capabilities for SystemC-AMS to describe energy conserving multi-domain systems in a formal and consistent way at a high level of abstraction. To this end, all variables and parameters of the system model need to be a ...
Ieee Service Center, 445 Hoes Lane, Po Box 1331, Piscataway, Nj 08855-1331 Usa2009
The modelling and simulation capabilities of SystemC-AMS concerning conservative continuous time systems involving the interaction of several physical domains and with digital control components are currently limited. Bond graphs unify the description of m ...
Systems-on-Chip (SoCs) are heterogeneous by nature as they may integrate digital, analog, RF hardware as well as software components or non electrical parts such as sensors or actuators. The increasing level of complexity for designing SoCs in a reasonable ...
In this paper, we demonstrate fixed-point FPGA implementations of state space systems using Particle Filters, especially multi-target beating and range tracking systems. These trackers operate either as independent organic trackers or as a joint tracker to ...
This paper presents a contribution to the development of rapid prototyping tools based on data-flow description. In this context, the efficiency of automatic translator tools from the data-flow description to C and/or HDL are presented using two design cas ...
There is a need to improve the modelling capabilities of SystemC-AMS concerning conservative continuous time systems involving the interaction of several physical domains and the interaction with digital control components. Bond graphs unify the descriptio ...
Fraunhofer Institut für Integrierte Schaltungen, Außenstelle Entwurfsautomatisierung2007
SystemC-AMS currently offers modelling formalisms with specialised solvers mainly focussing on the electrical domain. There is a need to improve its modelling capabilities concerning conservative continuous time systems involving the interaction of several ...
Networks on Chip (NoC) has been proposed as a scalable and reusable solution for interconnecting the ever- growing number of processor/memory cores on a single silicon die. As the hardware complexity of a NoC is significant, methods for designing a NoC wit ...
