Publications related to Flow to HDL

High level synthesis of Smith-Waterman dataflow implementations

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

The paper presents the results of design explorations for the implementation of the Smith-Waterman (S-W) algorithm executing DNA and protein sequences alignment. Both design explorations studies and the corresponding FPGA implementations are obtained by wr ...

2017

Automated Design Flow for Multi-Functional Dataflow-Based Platforms

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

The implementation of processing platforms supporting multiple applications by runtime reconfigurations on dedicated hardware modules requires the solution of different problems. These problems are notably not-trivial since both platform and application co ...

Springer Verlag2015

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits

Giovanni De Micheli, Pierre-Emmanuel Julien Marc Gaillardon, Jian Zhang, Shashi Kanth Bobba, Subhasish Mitra

The quest for technologies with superior device characteristics has showcased Carbon-Nanotube Field-Effect Transistors (CNFET) into limelight. In this work we present physical design techniques to improve the yield of CNFET circuits in the presence of Carb ...

Assoc Computing Machinery2014

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

Marco Mattavelli, Endri Bezati, Ghislain Roquier, Richard Thavot

The potential computational power of today multicore processors has drastically improved compared to the single processor architecture. Since the trend of increasing the processor frequency is almost over, the competition for increased performance has move ...

Springer Heidelberg2014

Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case

Marco Mattavelli, Simone Casale Brunet, Endri Bezati

Specialized hardware infrastructures for efficient multi-application runtime reconfigurable platforms require to address several issues. The higher is the system complexity, the more error prone and time consuming is the entire design flow. Moreover, syste ...

IEEE2014

Performance Optimization and FPGA Implementation of Real-Time Tone Mapping

Yusuf Leblebici, Vladan Popovic, Eliéva Arlette Pignat

This brief analyzes the performance of the hardware-based tone mapping operators for compression of high dynamic range images. The bottlenecks of a tone mapping system are determined and a high-performance field programmable gate array (FPGA) implementatio ...

Institute of Electrical and Electronics Engineers2014

Real-Time Processing System for the JET Hard X-Ray and Gamma-Ray Profile Monitor Enhancement

Patrick Blanchard

The Joint European Torus (JET) is currently undertaking an enhancement program which includes tests of relevant diagnostics with real-time processing capabilities for the International Thermonuclear Experimental Reactor (ITER). Accordingly, a new real-time ...

Ieee-Inst Electrical Electronics Engineers Inc2014

Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case

Andreas Peter Burg, Paolo Ienne, Georgios Karakonstantis, David Novo Bruna, Madhura Purnaprajna

Hardware designers and engineers typically need to explore a multi-parametric design space in order to ﬁnd the best conﬁguration for their designs using simulations that can take weeks to months to complete. For example, designers of special purpose chips ...

2012

Reliability of Nanoscale Circuits and Systems

Alexandre Schmid, Yusuf Leblebici, Milos Stanisavljevic

Reliability of Nanoscale Circuits and Systems: Methodologies and Circuit Architectures Milos Stanisavljevic Alexandre Schmid Yusuf Leblebici Future integrated circuits are expected to be made of emerging nanodevices and their associated interconnects, but ...

Springer2011

Chat with Graph Search

Ask any question about EPFL courses, lectures, exercises, research, news, etc. or try the example questions below.

DISCLAIMER: The Graph Chatbot is not programmed to provide explicit or categorical answers to your questions. Rather, it transforms your questions into API requests that are distributed across the various IT services officially administered by EPFL. Its purpose is solely to collect and recommend relevant references to content that you can explore to help you answer your questions.

Flow to HDL

High level synthesis of Smith-Waterman dataflow implementations

Automated Design Flow for Multi-Functional Dataflow-Based Platforms

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case

Performance Optimization and FPGA Implementation of Real-Time Tone Mapping

Real-Time Processing System for the JET Hard X-Ray and Gamma-Ray Profile Monitor Enhancement

Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case

Reliability of Nanoscale Circuits and Systems

Supporting Dimensional Analysis in SystemC-AMS

Graph Chatbot

Chat with Graph Search

High level synthesis of Smith-Waterman dataflow implementations

Real-Time Processing System for the JET Hard X-Ray and Gamma-Ray Profile Monitor Enhancement

Automated Design Flow for Multi-Functional Dataflow-Based Platforms

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case

Supporting Dimensional Analysis in SystemC-AMS

Reliability of Nanoscale Circuits and Systems

Performance Optimization and FPGA Implementation of Real-Time Tone Mapping

Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case