Formally Verified Chisel Designs

Related lectures (30)

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Explores synchronous logic circuits, state-based modeling, optimization techniques, and finite-state machine state minimization.

Covers principles of synchronous RTL design, custom digital circuits, Y-Diagram visualization, signal classes, and hierarchy management.

Covers the design of an Arbiter FSM in VHDL for digital system design, emphasizing access timing management.

Covers the design of a KeyLock system in VHDL, focusing on the FSM implementation for key validation and LED indication.

Explores static timing analysis in digital system design, covering setup and hold time requirements, critical paths, and timing conditions.

Introduces clocked systems, sequential circuits, bistable-state devices, metastable states, and D-type flip-flops.

Provides an overview of finite state machines, covering their design, analysis, and practical applications in digital systems.

Introduces the Stainless verification tool with examples of verifying commutativity properties and arithmetic operations.

Explores the Spec# programming system, focusing on a verifying compiler for C# 2.0.

Covers digital signal processing, binary and Boolean logic, and practical examples of digital circuits.