Lecture
SecChisel: Security Verification of Secure Processor Architectures
Description
This lecture introduces the SecChisel framework, which verifies security properties of secure processor architectures at design-time. It covers Chisel as a hardware construction language, information flow tracking, security lattices, security tags, FIRRTL, SMT-LIB, and evaluation using AES within a RISC-V Rocket Chip. The framework aims to detect information leaks and hardware bugs efficiently, without adding runtime components.
Official source
About this result
This page is automatically generated and may contain information that is not correct, complete, up-to-date, or relevant to your search query. The same applies to every other page on this website. Please make sure to verify the information with EPFL's official sources.