CMOS Circuit Design: Layout Optimization

In course

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Description

This lecture covers the practical exercise session on CMOS circuit design, focusing on layout optimization techniques. The session includes designing a common-centroid layout for an NMOS differential pair, sizing current source MOSFETs, simulating differential and common-mode gains, and analyzing circuit performance. Students will learn to iterate MOSFET sizing for optimal performance, understand the impact of resistor mismatches on gain, and design a CMOS circuit meeting specific specifications.

Instructor

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Official source

https://mediaspace.epfl.ch/media/0_8witdu2s

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Ontological neighbourhood

Computer engineering

Hardware engineering: Microprocessors, Application-specific integrated circuit

Physics

Electromagnetism: Electrical networks

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