Lecture

CMOS Circuit Design: Layout Optimization

Description

This lecture covers the practical exercise session on CMOS circuit design, focusing on layout optimization techniques. The session includes designing a common-centroid layout for an NMOS differential pair, sizing current source MOSFETs, simulating differential and common-mode gains, and analyzing circuit performance. Students will learn to iterate MOSFET sizing for optimal performance, understand the impact of resistor mismatches on gain, and design a CMOS circuit meeting specific specifications.

About this result
This page is automatically generated and may contain information that is not correct, complete, up-to-date, or relevant to your search query. The same applies to every other page on this website. Please make sure to verify the information with EPFL's official sources.