Layout of Analog CMOS IC

In course

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Description

This lecture covers the process of drawing a layout in Cadence, focusing on the layout of analog CMOS ICs. Topics include the use of multiple fingers, matching single transistors, parasitics in transistors, and asymmetry due to fabrication.

Instructor

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Official source

https://mediaspace.epfl.ch/media/0_5itaw8el

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