This lecture covers the process of drawing a layout in Cadence, focusing on the layout of analog CMOS ICs. Topics include the use of multiple fingers, matching single transistors, parasitics in transistors, and asymmetry due to fabrication.
This page is automatically generated and may contain information that is not correct, complete, up-to-date, or relevant to your search query. The same applies to every other page on this website. Please make sure to verify the information with EPFL's official sources.
Sunt cillum ipsum deserunt ea. Id ex officia proident aliqua anim irure mollit in incididunt duis. Officia consequat enim ipsum veniam reprehenderit Lorem nostrud eu.
Magna id proident Lorem veniam fugiat labore minim ut. Officia aliqua mollit aliquip do amet consequat duis culpa tempor culpa in id. Ea in labore veniam Lorem do dolor reprehenderit cillum dolor et. Consequat laborum Lorem laboris non qui amet commodo in nisi. Reprehenderit elit consectetur excepteur est sint eu commodo.
Covers the fundamentals of analog CMOS integrated circuits, emphasizing transistor-level design principles and the historical impact of CMOS technology.
