FPGA Architecture: LUT and Routing Arrays

This lecture covers the transition from CPLD to FPGA, focusing on the architecture of FPGAs. It explains the concept of Look Up Tables (LUTs) and their role in representing logic functions. The lecture also delves into the structure of routing arrays, which provide interconnectivity within the FPGA. It discusses the limitations of LUTs to four inputs and the scalability of FPGAs. Additionally, it explores the challenges of placement and routing in FPGA synthesis, emphasizing the importance of connecting inputs and outputs effectively. The evolving FPGA technology, reasons for using FPGAs, and practical applications are also addressed.