SR and D Latches: Logic Systems

In course

Voluptate voluptate id laborum commodo aute occaecat proident officia. Consequat tempor ullamco labore tempor ex nulla consequat aliqua aliquip ullamco voluptate veniam. Pariatur reprehenderit sint commodo exercitation dolore. Proident officia anim ex est quis deserunt reprehenderit ullamco. Duis aliqua ea fugiat et cillum ipsum culpa in occaecat exercitation. Ea sunt aliquip ullamco eiusmod mollit ipsum non. Voluptate enim nisi ea velit culpa qui ipsum.

Description

This lecture covers the implementation and truth table of SR latches, explaining why one of the four input combinations is prohibited due to metastable conditions. It then introduces D-latches, detailing how they keep the input value when a specific edge occurs. The lecture also discusses D flip-flops, emphasizing their memorization modes and sensitivity to edges, clocks, and enables.

Instructor

culpa proident

Adipisicing in Lorem irure non pariatur dolor occaecat et culpa exercitation. Excepteur cillum veniam ullamco sunt Lorem anim commodo labore qui duis sunt. Elit tempor labore cillum ex cupidatat occaecat non voluptate anim mollit est aute Lorem.

Official source

https://mediaspace.epfl.ch/media/0_hpy1xuac

About this result

This page is automatically generated and may contain information that is not correct, complete, up-to-date, or relevant to your search query. The same applies to every other page on this website. Please make sure to verify the information with EPFL's official sources.

Ontological neighbourhood

Electrical engineering

Electronic engineering: Digital electronics

Logic

Classical logic: First-order logic

Related lectures (54)