Lecture

Logical Effort: Fundamentals of VLSI Design

In course

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Description

This lecture covers the Logical Effort method for optimizing logic delay, including technology-independent delay models, intrinsic delay derivation, and gate sizing impact. It explains the path delay calculation with Logical Effort and provides examples of gate delay and gate sizing impact.

Instructor

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Official source

https://mediaspace.epfl.ch/media/0_obylqmi7

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Ontological neighbourhood

Electrical engineering

Electronic engineering: Digital electronics

Computer engineering

Hardware engineering: Microprocessors, Application-specific integrated circuit

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