Lecture
This lecture discusses the design and functionality of a three-layer camera that integrates a DRAM chip with a CMOS image sensor. The instructor explains the architecture of the camera, highlighting the role of the DRAM in storing images and facilitating high-speed readout. The lecture covers the concept of super slow motion, achieved by capturing images at 960 frames per second, while also maintaining the ability to output at standard speeds of 30 frames per second. The instructor details the signal processing involved, including the use of high-speed buses for data transfer and the importance of binning techniques to enhance image quality. The lecture also references a specific Sony CMOS image sensor, emphasizing its capabilities and applications in fields such as sports analysis. The presentation concludes with a demonstration of the super slow motion capabilities, showcasing the technology's potential without compromising image resolution, even during high-speed capture.