Publications by Paolo Ienne | EPFL Graph Search

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Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

Resource Sharing in Dataflow Circuits

Resource Sharing in Dataflow Circuits

From C/C plus plus Code to High-Performance Dataflow Circuits

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Scalable Fine-Grained Parallel Cycle Enumeration Algorithms

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

Resource Sharing in Dataflow Circuits

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

Resource Sharing in Dataflow Circuits

From C/C plus plus Code to High-Performance Dataflow Circuits

Scalable Fine-Grained Parallel Cycle Enumeration Algorithms

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits