Publications by Paolo Ienne | EPFL Graph Search

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Unleashing Parallelism in Elastic Circuits with Faster Token Delivery

How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System

FPGA Architecture: Principles and Progression

Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses

Turning PathFinder Upside -Down: 1-4,xploring FPGA Switch -Blocks by Negotiating Switch Presence

FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort

Buffer Placement and Sizing for High-Performance Dataflow Circuits

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths

Invited Tutorial Dynamatic: From C/C plus plus to Dynamically Scheduled Circuits