Paolo Ienne

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Publications associées (132)

Regularity Matters: Designing Practical FPGA Switch-Blocks

Paolo Ienne, Stefan Nikolic

Several techniques have been proposed for automatically searching for FPGA switch-blocks which typically show some tangible advantage over the well-known academic architectures. However, the resulting switch-blocks usually exhibit high levels of irregulari ...

Assoc Computing Machinery2023

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles

Paolo Ienne, Kubilay Atasu, Jovan Blanusa

Finding cycles in directed graphs enables important applications in various domains such as finance, biology, chemistry, and network science. However, as the size of graph datasets continues to grow, it becomes increasingly difficult to discover cycles wit ...

arXiv2023

Resource Sharing in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Axel Marmet

To achieve resource-efficient hardware designs, high-level synthesis (HLS) tools share (i.e., time-multiplex) functional units among operations of the same type. This optimization is typically performed in conjunction with operation scheduling to ensure th ...

Assoc Computing Machinery2023

Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Ayatallah Ahmed Gamal Kamal Elakhras

Dynamically scheduled high-level synthesis can exploit high levels of parallelism in poorly-predictable control-dominated applications. Yet, dataflow circuits are often generated by literal conversion of basic blocks into circuits interconnected in such a ...

Assoc Computing Machinery2023

Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles

Paolo Ienne, Kubilay Atasu, Jovan Blanusa

Cycles are one of the fundamental subgraph patterns and being able to enumerate them in graphs enables important applications in a wide variety of fields, including finance, biology, chemistry, and network science. However, to enable cycle enumeration in r ...

Assoc Computing Machinery2023

Introduction to the Special Section on FPGA 2022

Paolo Ienne

Assoc Computing Machinery2023

Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Paolo Ienne, Mikhail Asiatici

Applications such as large-scale sparse linear algebra and graph analytics are challenging to accelerate on FPGAs due to the short irregular memory accesses, resulting in low cache hit rates. Nonblocking caches reduce the bandwidth required by misses by re ...

ASSOC COMPUTING MACHINERY2022

Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Paolo Ienne, Grace Zgheib, Stefan Nikolic

In this work, we develop timing-driven CAD support for FPGA architectures with direct connections between LUTs. We do so by proposing an efficient ILP-based detailed placer, which moves a carefully selected subset of LUTs from their original positions, so ...

ASSOC COMPUTING MACHINERY2022

Scalable Fine-Grained Parallel Cycle Enumeration Algorithms

Paolo Ienne, Kubilay Atasu, Jovan Blanusa

2022

A Comprehensive Timing Model for Accurate Frequency Tuning in Dataflow Circuits

Paolo Ienne, Andrea Guerrieri, Lana Josipovic, Carmine Rizzi

The ability of dataflow circuits to implement dynamic scheduling promises to overcome the conservatism of static scheduling techniques that high-level synthesis tools typically rely on. Yet, the same distributed control mechanism that allows dataflow circu ...

IEEE COMPUTER SOC2022

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Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs

Paolo Ienne, Mikhail Asiatici

ASSOC COMPUTING MACHINERY2022