Publications by Paolo Ienne | EPFL Graph Search

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Exploiting Compute Caches for Memory Bound Vector Operations

Optimized Memory Access For Dynamically Scheduled High Level Synthesis

An Accelerator for High Efficient Vision Processing

Virtualized Execution Runtime for FPGA Accelerators in the Cloud

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains

An Out-of-Order Load-Store Queue for Spatial Computing

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element

Imprecise Security: Quality and Complexity Tradeoffs for Hardware Information Flow Tracking

Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays

Designing a Virtual Runtime for FPGA Accelerators in the Cloud