Marco Mattavelli

Related publications (286)

Toward a common standard for data and specimen provenance in life sciences

Anna Marsano, Marco Mattavelli

Open and practical exchange, dissemination, and reuse of specimens and data have become a fundamental requirement for life sciences research. The quality of the data obtained and thus the findings and knowledge derived is thus significantly influenced by the quality of the samples, the experimental methods, and the data analysis. Therefore, a comprehensive and precise documentation of the pre-analytical conditions, the analytical procedures, and the data processing are essential to be able to assess the validity of the research results. With the increasing importance of the exchange, reuse, and sharing of data and samples, procedures are required that enable cross-organizational documentation, traceability, and non-repudiation. At present, this information on the provenance of samples and data is mostly either sparse, incomplete, or incoherent. Since there is no uniform framework, this information is usually only provided within the organization and not interoperably. At the same time, the collection and sharing of biological and environmental specimens increasingly require definition and documentation of benefit sharing and compliance to regulatory requirements rather than consideration of pure scientific needs. In this publication, we present an ongoing standardization effort to provide trustworthy machine-actionable documentation of the data lineage and specimens. We would like to invite experts from the biotechnology and biomedical fields to further contribute to the standard.

WILEY2023

A Capacitively-Coupled Chopper Instrumentation Amplifier for Implantable Bridge Sensor Systems

Diego Ruben Barrettino, Mustafa Besirli, Catherine Dehollain, Marco Mattavelli, Kerim Türe

This paper presents an energy and area efficient capacitively-coupled chopper instrumentation amplifier (CCIA) dedicated to implantable bridge sensor systems. Chopper stabilization is employed to decrease its offset and 1/f noise and the resulting ripple due to the up-modulated offset and 1/f noise is suppressed by a switched-capacitor ripple reduction loop. The gain of the instrumentation amplifier is defined by a programmable capacitive feedback network with a gain range from 40 V/V to 116 V/V, which is suitable for use with bridge sensors having different output voltages. The proposed CCIA has been fabricated in a standard 0.18 mu m CMOS process. It achieves an input noise of 88.2 nV/root Hz, a worst-case input offset of 5 mu V, and an output ripple of less than 185 mu V. The CCIA occupies only 0.17 mm(2) chip area and draws 3.3 mu A current from a 1.2 V supply.

IEEE2022

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This paper presents an energy-efficient, duty-cycled, and spinning excitation bridge-to-digital converter (BDC) designed for implantable pressure sensing systems. The circuit provides the measure of the pulmonary artery pressure that is particularly relevant for the monitoring of heart failure and pulmonary hypertension patients. The BDC is made of a piezoresistive pressure sensor and a readout integrated circuit (IC) that comprises an instrumentation amplifier (IA) followed by an analog-to-digital converter (ADC). The proposed design spins both the bridge excitation and the ADC’s sampling input voltages simultaneously and exploits duty cycling to reduce the static power consumption of the bridge sensor and IA while cancelling the IA’s offset and 1/f noise at the same time. The readout IC has been designed and fabricated in a standard 180-nm CMOS process and achieves 8.4 effective number of bits (ENOB) at 1 kHz sampling rate while drawing 0.53 µA current from a 1.2 V supply. The BDC, built with the readout IC and a differential pressure sensor having 5 kΩ bridge resistances, achieves 0.44 mmHg resolution in a 270 mmHg pressure range at 1 ms conversion time. The current consumption of the bridge sensor by employing duty cycling is reduced by 99.8% thus becoming 0.39 µA from a 1.2 V supply. The total conversion energy of the pressure sensing system is 1.1 nJ, and achieves a figure-of-merit (FoM) of 3.3 pJ/conversion, which both represent the state of the art.

2022

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This paper presents a novel method for the measure of the cross-sectional area (CSA) of an artery to be used for the direct and continuous (24/7) monitoring of cardiac output (CO). The method is based on the inductance change of an anchoring loop mounted on a miniaturized system implanted in a section of the pulmonary artery. The inductive sensor comprises an inductive readout circuit and a conductive anchoring loop, which changes its inductance according to the deformation of the artery and can be correlated to the diameter and CSA of the artery section. Direct and periodic measurement of the CSA can improve the accuracy of CO monitoring in heart failure patients. An oscillator-based inductive readout IC was realized in a 180-nm CMOS process and the anchoring loop was implemented by a nitinol wire. The readout IC achieves 0.42 nH inductance resolution in a range from 181 nH to 681 nH and draws 39.7 μA to 51.2 μA current from a 1.2 V supply. The correlation between the artery diameter and loop inductance is demonstrated and the sensor achieves 0.24 mm resolution in a diameter range from 20 mm to 30 mm, a factor of four higher than the lateral resolution of echocardiography.

IEEE2022

Cardiovascular monitoring system

Diego Ruben Barrettino, Mustafa Besirli, Catherine Dehollain, Marco Mattavelli, Kerim Türe

A cardiovascular monitoring system for measuring at least cardiac output comprises an implantable unit (2) configured for placement in a section of artery of a patient and a portable external unit (1) configured for mounting against or close to a patient's skin for bidirectional communication with the implantable unit. A cross- sectional area measurement sensor (8) includes at least one elastic conductive loop (15, 15a, 15b) and an electronic circuit (16) connected to the conductive loop configured to measure an inductance value of the conductive loop. At least one ultrasound transducer (7,11) is further configured to measure a velocity of blood flow based on a Doppler effect.

2022

Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis

Aurélien François Gilbert Bloch, Simone Casale Brunet, Marco Mattavelli

Developing and fine-tuning software programs for heterogeneous hardware such as CPU/GPU processing platforms comprise a highly complex endeavor that demands considerable time and effort of software engineers and requires evaluating various fundamental components and features of both the design and of the platform to maximize the overall performance. The dataflow programming approach has proven to be an appropriate methodology for reaching such a difficult and complex goal for the intrinsic portability and the possibility of easily decomposing a network of actors on different processing units of the heterogeneous hardware. Nonetheless, such a design method might not be enough on its own to achieve the desired performance goals, and supporting tools are useful to be able to efficiently explore the design space so as to optimize the desired performance objectives. This article presents a methodology composed of several stages for enhancing the performance of dataflow software developed in RVC-CAL and generating low-level implementations to be executed on GPU/CPU heterogeneous hardware platforms. The stages are composed of a method for the efficient scheduling of parallel CUDA partitions, an optimization of the performance of the data transmission tasks across computing kernels, and the exploitation of dynamic programming for introducing SIMD-capable graphics processing unit systems. The methodology is validated on both the quantitative and qualitative side by means of dataflow software application examples running on platforms according to various different mapping configurations.

MDPI2022

Inter-actions parallel execution on GPU from high-level dataflow synthesis

Aurélien François Gilbert Bloch, Simone Casale Brunet, Marco Mattavelli

Recent GPU architectures make available numbers of parallel processing units that exceed by orders of magnitude the ones offered by CPU architectures. Whereas programs written using dataflow programming languages are well suited for programming heterogeneous systems, they might not offer sufficient parallel degrees to efficiently exploit the resources available on today’s GPUs. This paper describes how the extension of a dataflow-based approach for the synthesis of programs to be executed on mixed CPU and GPU architectures can increase the parallelism of executions on GPU. The extended approach consists of a new methodology for scheduling, in parallel, the execution of actors’ actions that uses the hardware resources available on modern GPU more efficiently. This is possible without imposing any limitation on the dataflow model of computation (MoC) of the network, all fully dynamic MoCs are supported. The paper also introduces relevant features of recent NVidia GPUs used by this approach and describes how they are used to allow dynamic reconfiguration of the execution which dynamically reconfigure the level of parallelism of actual actor execution. The paper also justifies and explains the necessity for a specially designed FIFO buffer that both preserve the dataflow computational model, and enables full parallel data accesses.

IEEE2022

MPEG-G Reference-Based Compression of Unaligned Reads Through Ultra-Fast Alignments

Simone Casale Brunet, Marco Mattavelli, Ünsal Öztürk

IEEE2022

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms

Aurélien François Gilbert Bloch, Simone Casale Brunet, Marco Mattavelli

The performance of programs written in languages following the dataflow model of computation (MoC) largely depends on the configuration (partitioning, mapping, scheduling, buffer dimensioning) chosen during the synthesis stages. Furthermore, this programming paradigm is particularly well suited for heterogeneous parallel systems because it is inherently free of memory contention and exposes parallel opportunities. Both of these statements show the necessity for a way to easily and automatically evaluate and find good design configurations. The paper describes the methodology required for clock-accurate profiling of high-level dataflow programs written in RVL-CAL when synthesized on heterogeneous CPU/GPU co-processing platforms. It also extends to the heterogeneous paradigm an existing methodology for qualitatively estimating the performance of such programs as a function of the provided configuration. This, without the need to synthesize and profile every single configuration on the actual hardware platform. This approach is validated using two application programs and several configurations.

2022

Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution

Aurélien François Gilbert Bloch, Simone Casale Brunet, Marco Mattavelli

The performance of programs executed on heterogeneous parallel platforms largely depends on the design choices regarding how to partition the processing on the various different processing units. In other words, it depends on the assumptions and parameters that define the partitioning, mapping, scheduling, and allocation of data exchanges among the various processing elements of the platform executing the program. The advantage of programs written in languages using the dataflow model of computation (MoC) is that executing the program with different configurations and parameter settings does not require rewriting the application software for each configuration setting, but only requires generating a new synthesis of the execution code corresponding to different parameters. The synthesis stage of dataflow programs is usually supported by automatic code generation tools. Another competitive advantage of dataflow software methodologies is that they are well-suited to support designs on heterogeneous parallel systems as they are inherently free of memory access contention issues and naturally expose the available intrinsic parallelism. So as to fully exploit these advantages and to be able to efficiently search the configuration space to find the design points that better satisfy the desired design constraints, it is necessary to develop tools and associated methodologies capable of evaluating the performance of different configurations and to drive the search for good design configurations, according to the desired performance criteria. The number of possible design assumptions and associated parameter settings is usually so large (i.e., the dimensions and size of the design space) that intuition as well as trial and error are clearly unfeasible, inefficient approaches. This paper describes a method for the clock-accurate profiling of software applications developed using the dataflow programming paradigm such as the formal RVL-CAL language. The profiling can be applied when the application program has been compiled and executed on GPU/CPU heterogeneous hardware platforms utilizing two main methodologies, denoted as static and dynamic. This paper also describes how a method for the qualitative evaluation of the performance of such programs as a function of the supplied configuration parameters can be successfully applied to heterogeneous platforms. The technique was illustrated using two different application software examples and several design points.

MDPI2022