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Maher Kayal

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OTA-C based high-speed analog processing for real-time fault location in electrical power networks

Maher Kayal, François Krummenacher, François Pierre Gaugaz

This paper explores the potential and limitations of analog integrated circuit techniques for the simulation of low-loss or lossless 1D or 2D transmission mediums. In this approach, a transmission line is mapped into a ladder consisting of N identical LC e ...

Springer Verlag2016

Implementation Guidelines for a Real-Time Fault Location System in Electrical Power Networks

Maher Kayal, François Krummenacher, François Pierre Gaugaz

This paper presents constraints involved in the microelectronic implementation of a transmission line model based on transconductor-capacitor (gm-C) topologies. The presented line model, based on the discretization of a transmission line into a finite numb ...

Ieee2016

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Today circuit failures in Smart Power ICs due to substrate couplings are partially addressed during the circuit design phase. The state-of-the-art guidelines for the optimization of parasitic couplings provide mainly qualitative rules, which are difficult ...

Institute of Electrical and Electronics Engineers2016

Building Virtualization Engine: a Novel Approach Based on Discrete Event Simulation

Maher Kayal, Georgios Lilis, Olivier Valentin Henri Van Cutsem

This paper proposes and validates a Discrete Event Simulation (DES) engine for the Smart-Building (SB). It strives to virtualize the common elements found within it and integrates them transparently to an existing Building Management System (BMS), along wi ...

Ieee2016

Event-driven Human Based Evolutionary Knowledge Base for Smart Buildings

Maher Kayal, Nastaran Asadi Zanjani

This paper presents an approach to automatically create a knowledge base for smart buildings and let it dynamically evolve based on the behaviors of the occupants inside. Such a knowledge base compromises all life-style experiences and intelligent building ...

Ieee2016

Analysis of Substrate Currents Propagation in HVCMOS technology

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

This work reports the results of a layout-aware substrate modeling methodology for HVCMOS technologies. The model relies on the extraction of parasitic substrate network to simulate with circuit software parasitic lateral NPN bipolar transistors with multi ...

IEEE2016

A nA Crystal - Less Oscillator for Internet of Things

Maher Kayal, François Krummenacher, Mathieu Yves Hervé Coustans

This work presents an ultra-low power oscillator designed to target different contexts, such as crystal-assisted time keeping, reference oscillator to optimize the always on domain of a microcontroller or wake-up timer. This oscillator enables ultra-low po ...

Ieee2016

A 400 fJ Per-Cycle Frequency Reference for Internet of Things

Maher Kayal, François Krummenacher, Mathieu Yves Hervé Coustans

2016

Distributed Intelligent Modules System Using Power-line Communication for Electrical Appliance Automation

Maher Kayal, Laurent Fabre, Fabrizio Lo Conte, Thierry Barras

In a first aspect the invention provides a system that comprising a plurality of electronic modules, each one of the electronic modules configured for enabling automation of an electrical appliance to be connected to the electronic module. Each electronic ...

2016

Spice-compatible modeling of high injection and propagation of minority carriers in the substrate of Smart Power ICs

Maher Kayal, Jean-Michel Sallese, Camillo Stefanucci, Pietro Buccella

Classical substrate noise analysis considers the silicon resistivity of an integrated circuit only as doping dependent besides neglecting diffusion currents as well. In power circuits minority carriers are injected into the substrate and propagate by drift ...

Elsevier2015

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Building Virtualization Engine: a Novel Approach Based on Discrete Event Simulation

Maher Kayal, Georgios Lilis, Olivier Valentin Henri Van Cutsem

Ieee2016

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Institute of Electrical and Electronics Engineers2016

Simulation, Analysis, and Verification of Substrate Currents for Layout Optimization of Smart Power ICs