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Yusuf Leblebici

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Yusuf Leblebici

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A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links

Real-time high-resolution omnidirectional imaging platform for drone detection and tracking

Switching Kinetics Control of W-Based ReRAM Cells in Transient Operation by Interface Engineering

Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS

Real-Time Textureless-Region Tolerant High-Resolution Depth Estimation System

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

Adaptive Learning-Based Compressive Sampling for Low-power Wireless Implants