Yusuf Leblebici

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Related publications (405)

Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization

Elmira Shahrabi, Thomas La Grange, Yusuf Leblebici, Tugba Demirci

The integration of the resistive random access memory (ReRAM) with CMOS logic circuitry provides a solution to scaling limitations, and offers promising candidates for use in next generation computing applications. It is challenging to realize a reliable, ...

ELSEVIER SCIENCE BV2019

MPA-SSA, design and test of a 65 nm ASIC-based system for particle tracking at HL-LHC featuring on-chip particle discrimination

Yusuf Leblebici, Alessandro Caratelli, Davide Ceresa, Simone Scarfì

Particle tracking detectors for High Energy Physics need a new readout technique to cope with the increase of the collision rate foreseen for the High Luminosity LHC upgrade. In particular, the selection of interesting physics events at the first trigger s ...

IEEE2019

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS

Andreas Peter Burg, Seyed Armin Tajalli, Yusuf Leblebici, Firat Çelik, Ayça Akkaya

JESD204B compliant low-voltage differential signaling (LVDS), and source-series-terminated (SST) transmitters in 28 nm FD-SOI CMOS technology are presented with 1.1 pJ/bit and 1.7 pJ/bit at 12.5 Gb/s, respectively. An external 6.25 GHz single-ended clock, ...

IEEE2019

ISI Sensitivity of PAM Signaling for Very High-Speed Short-Reach Copper Links

Yusuf Leblebici, Seyed Armin Tajalli, Firat Çelik, Ayça Akkaya

This paper presents a comparative study, analyzing the potentials of pulse amplitude modulation (PAM) for implementing next generation high-speed copper wireline links. This comparative study analyzes the sensitivities of PAM2, PAM4 and PAM8 to inter-symbo ...

IEEE2019

Non-filamentary non-volatile memory elements as synapses in neuromorphic systems

Yusuf Leblebici, Alessandro Fumarola, Severin Sidler

Crossbar arrays of non-volatile memory (NVM) devices represent one possible path for implementing highly energy-efficient neuromorphic computing systems. For Deep Neural Networks (DNN), where information can be encoded as analog voltage and current levels, ...

IEEE2019

A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET

Andreas Peter Burg, Cosimo Aprile, Yusuf Leblebici, Alessandro Cevrero, Gain Kim, Lukas Kull, Ilter Ozkaya, Thomas Toifl

This work presents an ADC-bascd receiver (RX) data-path for frame-based PAM-4 modulation with a cyclic prefix (CP). Similar to discrete multi-tone (DMT) modulation, a frame of PAM-4 symbols arc protected from the channel delay spread by the CP taps. A PAM- ...

IEEE2019

Switching Kinetics Control of W-Based ReRAM Cells in Transient Operation by Interface Engineering

Thomas La Grange, Yusuf Leblebici, Mahmoud Hadad, Carlo Ricciardi, Cecilia Giovinazzo, Miguel Ramos

Tungsten (W) is one of the most promising materials to be used in resistive random-access memory electrodes due to its low work function and compatibility with semiconductors, which raises the possibility of device integration, scalability, and low power c ...

WILEY2019

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications

Andreas Peter Burg, Robert Giterman, Cosimo Aprile, Yusuf Leblebici, Andrea Bonetti, Jonathan Emmanuel D Narinx, Nicolas Claude Frigerio

Logic-compatible gain-cell embedded DRAM (GC-eDRAM) is an emerging alternative to conventional SRAM for memory-dominated system-on-chip (SoC) designs due to its high-density, low-power, and two-ported operation. Although GCs have a limited data retention t ...

IEEE2019

Design Considerations and Performance Trade-Offs for 56Gb/s Discrete Multi-Tone Electrical Link

Yusuf Leblebici, Gain Kim, Thomas Toifl

For communicating over mid-to-long-reach electrical links at a data-rate above 56Gb/s, ADC-based receiver (RX) has become a dominant architecture due to its strong equalization capability using complex digital signal processing algorithm benefiting from th ...

IEEE2019

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

Andreas Peter Burg, Cosimo Aprile, Yusuf Leblebici, Alessandro Cevrero, Gain Kim, Lukas Kull, Ilter Ozkaya, Thomas Toifl

IEEE2019

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Performance improvement of chip-level CMOS-integrated ReRAM cells through material optimization

Elmira Shahrabi, Thomas La Grange, Yusuf Leblebici, Tugba Demirci

ELSEVIER SCIENCE BV2019

MPA-SSA, design and test of a 65 nm ASIC-based system for particle tracking at HL-LHC featuring on-chip particle discrimination

Yusuf Leblebici, Alessandro Caratelli, Davide Ceresa, Simone Scarfì

IEEE2019