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Yusuf Leblebici

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Yusuf Leblebici

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A Power-Efficient Clock and Data Recovery Circuit in 0.18-um CMOS Technology for Multi-Channel Short-Haul Optical Data Communication

Tradeoffs in Design of Low-Power Gated-Oscillator CDR Circuits

Fault-Tolerant Logic Gates Using Neuromorphic CMOS Circuits

CMOS Multi-Channel Single-Chip Receivers for Multi-Gigabit Optical Data Communications

Ultra Low Power Subthreshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept

A Power-Efficient LVDS Driver Circuit in 0.18-um CMOS Technology

Design of Completion Detection Circuits for Self-timed Systems Operating in Subthreshold Regime

Current Sensing Completion Detection for Subthreshold Asynchronous Circuits

A Methodology for Reliability Enhancement of Nanometer- Scale Digital Systems Based on A-Priori Functional Fault- Tolerance Analysis

Design and Realization of a Fault-Tolerant 90nm Cryptographic Engine Capable of Performing under Massive Defect Density