Publications by Philip Brisk | EPFL Graph Search

A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer

Mirjana Stojilovic, Philip Brisk, Frédéric Gessler

RePlAce is a state-of-the-art prototype of a flat, analytic, and nonlinear global cell placement algorithm, which models a placement instance as an electrostatic system with positively charged objects. It can handle large-scale standard-cell and mixed-cell ...

IEEE2020

Deterministic Parallel Routing for FPGAs based on Galois Parallel Execution Model

Mirjana Stojilovic, Philip Brisk

This paper describes a deterministic and parallel implementation of the VPR routability-driven router for FPGAs. We considered two parallefization strategies: (1) routing multiple nets in parallel; and (2) routing one net at a time, while parallelizing the ...

IEEE2018

An Out-of-Order Load-Store Queue for Spatial Computing

Paolo Ienne, Lana Josipovic, Philip Brisk

The efficiency of spatial computing depends on the ability to achieve maximal parallelism. This necessitates memory interfaces that can correctly handle memory accesses that arrive in arbitrary order while still respecting data dependencies and ensuring ap ...

Assoc Computing Machinery2017

From C to elastic circuits

Paolo Ienne, Lana Josipovic, Philip Brisk

2017

Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking

Paolo Ienne, Philip Brisk, Andrew James Becker, Ryan Charles Kastner, Wei Hu

2017

Automatic Application of Power Analysis Countermeasures

Paolo Ienne, Francesco Regazzoni, Ali Galip Bayrak, Philip Brisk, David Novo Bruna

We introduce a compiler that automatically inserts software countermeasures to protect cryptographic algorithms against power-based side-channel attacks. The compiler first estimates which instruction instances leak the most information through side-channe ...

Institute of Electrical and Electronics Engineers2015

Virtual Ways: Low-Cost Coherence for Instruction Set Extensions with Architecturally Visible Storage

Edoardo Charbon, Paolo Ienne, Ties Jan Henderikus Kluter, Samuel Burri, Philip Brisk

Instruction set extensions (ISEs) improve the performance and energy consumption of application-specific processors. ISEs can use architecturally visible storage (AVS), localized compiler-controlled memories, to provide higher I/O bandwidth than reading da ...

Assoc Computing Machinery2014

Way Stealing: A Unified Data Cache and Architecturally Visible Storage for Instruction Set Extensions

Edoardo Charbon, Paolo Ienne, Ties Jan Henderikus Kluter, Philip Brisk

Way Stealing is a simple architectural modification to a cache-based processor that increases the data bandwidth to and from application-specific instruction set extensions (ISEs), which increase performance and reduce energy consumption. Way Stealing offe ...

Institute of Electrical and Electronics Engineers2014

Generalized programmable counter arrays

Philip Brisk, Alessandro Cevrero, Hadi Parandeh Afshar

A Generalized Programmable Counter Array (GPCA) is a reconfigurable multi-operand adder, which can be reprogrammed to sum a plurality of operands of arbitrary size. The GPCA is configured to compress the input words down to two operands using parallel coun ...

2014

Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays

Paolo Ienne, Mirjana Stojilovic, Philip Brisk, David Novo Bruna

Historically, hardware acceleration technologies have either been application-specific, therefore lacking in flexibility, or fully programmable, thereby suffering from notable inefficiencies on an application-by-application basis. To address the growing ne ...

Institute of Electrical and Electronics Engineers2013