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Babak Falsafi

Related publications (151)

Cooperative Concurrency Control for Write-Intensive Key-Value Workloads

Babak Falsafi, Alexandros Daglis, Mark Johnathon Sutherland

Key-Value Stores (KVS) are foundational infrastructure components for online services. Due to their latency-critical nature, today’s best-performing KVS contain a plethora of full-stack optimizations commonly targeting read-mostly, popularity-skewed worklo ...

ACM2023

SecureCells: A Secure Compartmentalized Architecture

Babak Falsafi, Mathias Josef Payer, Yuanlong Li, Florian Hofhammer, Siddharth Gupta, Atri Bhattacharyya, Andrés Sánchez Marín

Modern programs are monolithic, combining code of varied provenance without isolation, all the while running on network-connected devices. A vulnerability in any component may compromise code and data of all other components. Compartmentalization separates ...

2023

Imprecise Store Exceptions

Babak Falsafi, Mathias Josef Payer, Yuanlong Li, Siddharth Gupta, Yunho Oh, Qingxuan Kang, Abhishek Bhattacharjee

Precise exceptions are a cornerstone of modern computing as they provide the abstraction of sequential instruction execution to programmers while accommodating microarchitectural optimizations. However, increasing compute capabilities in deep memory hierar ...

ACM2023

AstriFlash: A Flash-Based System for Online Services

Babak Falsafi, Lei Yan, Siddharth Gupta, Mark Johnathon Sutherland, Yunho Oh

Modern datacenters host datasets in DRAM to offer large-scale online services with tight tail-latency requirements. Unfortunately, as DRAM is expensive and increasingly difficult to scale, datacenter operators are forced to consider denser storage technolo ...

2022

Rebooting Virtual Memory with Midgard

Babak Falsafi, Mathias Josef Payer, Siddharth Gupta, Atri Bhattacharyya, Yunho Oh, Abhishek Bhattacharjee

Computer systems designers are building cache hierarchies with higher capacity to capture the ever-increasing working sets of modern workloads. Cache hierarchies with higher capacity improve system performance but shift the performance bottleneck to addres ...

2021

Data transformer apparatus

Babak Falsafi, Christoph Koch, Siddharth Gupta, Mario Paulo Drumond Lages De Oliveira, Mark Johnathon Sutherland, Arash Pourhabibi Zarandi, Zilu Tian, Hussein Kassir

Data transformer apparatus comprising at least a dispatcher module (D), a reader module (R), a converter module (C) and a writer module (W). The dispatcher module (D) is configured to: receive a data transformation request (DTR) including: a first informat ...

2021

Equinox: Training (for Free) on a Custom Inference Accelerator

Babak Falsafi, Martin Jaggi, Louis Coulon, Ahmet Caner Yüzügüler, Mario Paulo Drumond Lages De Oliveira, Arash Pourhabibi Zarandi

DNN inference accelerators executing online services exhibit low average loads because of service demand variability, leading to poor resource utilization. Unfortunately, reclaiming idle inference cycles is difficult as other workloads can not execute on a ...

ACM2021

Exploiting Errors for Efficiency: A Survey from Circuits to Applications

Babak Falsafi, Alexandros Daglis, Eva Darulova, Mattia Cacciotti, Damien Zufferey, Sasa Misailovic

When a computational task tolerates a relaxation of its specification or when an algorithm tolerates the effects of noise in its execution, hardware, system software, and programming language compilers or their runtime systems can trade deviations from cor ...

ASSOC COMPUTING MACHINERY2020

The NEBULA RPC-Optimized Architecture

Babak Falsafi, Alexandros Daglis, Siddharth Gupta, Mark Johnathon Sutherland, Dionysios Pnevmatikatos

Large-scale online services are commonly structured as a network of software tiers, which communicate over the datacenter network using RPCs. Ongoing trends towards software decomposition have led to the prevalence of tiers receiving and generating RPCs wi ...

2020

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators

Babak Falsafi, Javier Picorel Obando, Abhishek Bhattacharjee

Virtual memory (VM) is critical to the usability and programmability of hardware accelerators. Unfortunately, implementing accelerator VM efficiently is challenging because the area and power constraints make it difficult to employ the large multi-level TL ...

2020

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