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Lukas Kull

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Lukas Kull

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A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

A 64Gb/s 1.4pJ/b NRZ Optical-Receiver Data-Path in 14nm CMOS FinFET

A 60 Gb/s 1.9 pJ/bit NRZ Optical-Receiver with Low Latency Digital CDR in 14nm CMOS FinFET

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

A 4.1 pJ/b 25.6 Gb/s 4-PAM Reduced-State Sliding-Block Viterbi Detector in 14 nm CMOS

Implementation of Low-Power 6–8 b 30–90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS