Publications de Lukas Kull | EPFL Graph Search

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

Andreas Peter Burg, Cosimo Aprile, Yusuf Leblebici, Alessandro Cevrero, Gain Kim, Lukas Kull, Ilter Ozkaya, Thomas Toifl

This article introduces a wireline receiver (RX) data-path employing discrete multi-tone (DMT) modulation for communicating over electrical links. The DMT RX incorporates a fully digital equalization data-path, with a synthesized and automatically placed a ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2020

A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET

Andreas Peter Burg, Cosimo Aprile, Yusuf Leblebici, Alessandro Cevrero, Gain Kim, Lukas Kull, Ilter Ozkaya, Thomas Toifl

This work presents an ADC-bascd receiver (RX) data-path for frame-based PAM-4 modulation with a cyclic prefix (CP). Similar to discrete multi-tone (DMT) modulation, a frame of PAM-4 symbols arc protected from the channel delay spread by the CP taps. A PAM- ...

IEEE2019

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

Andreas Peter Burg, Cosimo Aprile, Yusuf Leblebici, Alessandro Cevrero, Gain Kim, Lukas Kull, Ilter Ozkaya, Thomas Toifl

IEEE2019

A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET

Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Ilter Ozkaya, Thomas Toifl

2018

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

Andreas Peter Burg, Lukas Kull, Thomas Toifl, Giovanni Cherubini

The implementation of a 25.6-Gb/s four-level pulse-amplitude-modulation (4-PAM) reduced-state sliding-block Viterbi detector (VD) is presented. The power consumption of the VD is 105 orilV at a supply voltage of 0.7 V, corresponding to an energy efficiency ...

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2018

A 56Gb/s Burst-Mode NRZ Optical Receiver with 6.8ns Power-On and CDR-Lock Time for Adaptive Optical Links in 14nm FinFET CMOS

Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Ilter Ozkaya, Thomas Toifl

IEEE2018

Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

Cosimo Aprile, Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Gain Kim, Ilter Ozkaya, Thomas Toifl

This paper presents a parallel implementation technique of digital equalizer for high-speed wireline serial link receiver (RX). In wireline RX, inter-symbol interference (ISI) is mitigated by continuous-time linear equalizer, and the remaining ISI is cance ...

2018

A 112Gb/s 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

Alessandro Cevrero, Lukas Kull, Ilter Ozkaya, Thomas Toifl

IEEE2018

A 24-to-72GS/s 8b Time-Interleaved SAR ADC with 2.0-to-3.3pJ/conversion and > 30dB SNDR at Nyquist in 14nm CMOS FinFET

Alessandro Cevrero, Lukas Kull, Ilter Ozkaya, Thomas Toifl

IEEE2018

An Eight lanes 7Gb/s/pin Source Synchronous Single-Ended RX with Equalization and Far-End Crosstalk Cancellation for Backplane Channels

Volkan Cevher, Cosimo Aprile, Yusuf Leblebici, Alessandro Cevrero, Lukas Kull, Thomas Toifl

This paper presents a versatile crosstalk cancellation scheme for single-ended multi-lane backplane links. System-level investigations show that a scheme, which combines analog filters and decision-feedback crosstalk compensation on the receiver (RX) side ...

2018