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Person# Shenjie Wang

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Related research domains (2)

Analog-to-digital converter

In electronics, an analog-to-digital converter (ADC, A/D, or A-to-D) is a system that converts an analog signal, such as a sound picked up by a microphone or light entering a digital camera, into a digital signal. An ADC may also provide an isolated measurement such as an electronic device that converts an analog input voltage or current to a digital number representing the magnitude of the voltage or current. Typically the digital output is a two's complement binary number that is proportional to the input, but there are other possibilities.

Noise figure

Noise figure (NF) and noise factor (F) are figures of merit that indicate degradation of the signal-to-noise ratio (SNR) that is caused by components in a signal chain. These figures of merit are used to evaluate the performance of an amplifier or a radio receiver, with lower values indicating better performance. The noise factor is defined as the ratio of the output noise power of a device to the portion thereof attributable to thermal noise in the input termination at standard noise temperature T0 (usually 290 K).

Related publications (5)

Catherine Dehollain, Shenjie Wang

This paper presents the design and implementation of a 46-kS/s CMOS switch-capacitor dual-mode capacitive sensor interface circuit for inkjet-printed capacitive humidity sensors. The specifications of the interface circuit, which includes a capacitance-to-voltage (C2V) converter combined with an analog-to-digital converter (ADC), are optimized at system level, emphasizing the C2V operation followed by the data converter. A closed form of the maximum output range of a single-stage C2V is provided to prevent cascade amplification. The gain-boosting technique is utilized in the operational transconductance amplifier design to improve the closed-loop linearity. The correlated double sampling technique attenuates the dc offset and low-frequency flicker noise from C2V. A 10-b successive approximation register ADC digitizes the output of C2V. The total area of the digital-to-analog (DAC) array is limited not only by the matching behavior, but also by the noise performance of C2V. The rail-to-rail ability is required to render the compatibility with various possible sensor inputs. A single-ended cascaded binary-weighted capacitive DAC is used to implement the charge redistribution binary search algorithm. The circuit is implemented in a 0.18- mu m CMOS technology and occupies an area of 1.2 mm(2). The tested prototype shows 0.69% nonlinearity in mode 1 and 1.38% nonlinearity in mode 2. The SNR of mode 1 is 50.1 dB and that of mode 2 is 36.5 dB, which meets the specification of 7.32 b in mode 1 and 5.32 b in mode 2. The total power consumption of the capacitive sensor interface is 70 mu W.

As CMOS processes continue to scale to smaller dimensions, the increased fT of the devices and smaller parasitic capacitance allow formore power efficient and faster digital circuits to be made. But at the same time, output impedance of transistors has gone down, as have the power supply voltages, and leakage currents have increased. These changes in the technology havemade analog design more difficult.More specifically, the design of a high gain op-amp, a fundamental analog building block, has becomemore difficult in scaled processes. In this work, to improve the performance considering the speed, accuracy and power consumption of the analog-digital interface, both system level optimization and circuit level technique are explored. At first, a generalized graphic model (GGM) is proposed to analyze the resolution of ADC for wireless receiver. This model could show the trade-off between ADC the RF front-end in the power level graph. As a result, the optimization between them becomes practical. Next, two kinds of open loop ADCs are designed and implemented for ultra-wide bandwidth (UWB) receiver and capacitive sensor interface respectively. There is no closed loop stage in the flash ADC, which ensures the fastest conversion speed. An intended spatial filter technique is adopted to attenuate the distortion coming from the interpolation network. The successive approximation (SAR) ADC based switched capacitor sensor interface digitizes the capacitance variation to binary code. A cascade binary weighted DAC is used to reduce the power consumption and area. The noise and distortion performance are optimized throughout the design.

Catherine Dehollain, Shenjie Wang

This paper presents the design and implementation of a rail-to-rail 460-kS/s 10-bit successive approximation register analog-to-digital converter (ADC) for the power-efficient capacitance measurement. The specifications of ADC are optimized at system level, emphasizing the ADC following a switched-capacitor capacitance-to-voltage (C2V) converter. To be compatible to the output of C2V, a bootstrap switch with body effect reduction is adopted to provide the rail-to-rail processing ability. The charge redistribution converter is implemented by a single-ended cascaded binary-weighted capacitive digital-to-analog converter (DAC). The total area of the DAC array is not only limited by the matching behavior but also by the noise performance of C2V. To relax the settling requirement and improve the power efficiency, self-timing technique is employed which borrows extra half clock period for open-loop settling of preamps. The balance between noise and power consumption of dynamic comparator with preamps is also considered. The ADC circuit was implemented in 0.18-mu m CMOS technology and occupies an active area of 0.18 mm(2). The tested prototype achieves a signal-to-noise-plus-distortion ratio of 54 dB and a spurious-free dynamic range of 68 dB. The integral nonlinearity and differential nonlinearity are 0.5 and 0.34 least-significant-bit, respectively. The total power consumption is 21 mu W corresponding to 110 fJ/conversion-step figure of merit.