Publications by Sahand Kashani

A 475 MHz Manycore FPGA Accelerator for RTL Simulation

This paper presents the implementation of Manticore: a manycore accelerator for parallel RTL simulation. Manticore packs up to 225 custom soft processors running at 475 MHz on a large FPGA. Implementing manycore accelerators on FPGAs is challenging as desi ...

Association for Computing Machinery, Inc2024

Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism

James Richard Larus, Sahand Kashani

The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of this hardware depend heavily upon cycle-accurate simulation of register-transfer-level (RTL) designs. The ...

Assoc Computing Machinery2023

Building Chips Faster: Hardware-Compiler Co-Design for Accelerated RTL Simulation

Sahand Kashani

The demise of Moore's Law and Dennard scaling has resulted in diminishing performance gains for general-purpose processors, and so has prompted a surge in academic and commercial interest for hardware accelerators. Specialized hardware has already redefine ...

EPFL2023

Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats

James Richard Larus, Sahand Kashani

As the usage of FPGAs spreads, engineers will inevitably employ them in ways unforeseen-or unwanted-by their manufacturers. Xilinx's toolchains offer multiple points for customizing the FPGA compilation flow, but all flows must end with Vivado as it is the ...

IEEE COMPUTER SOC2022

Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips

Paolo Ienne, Andrea Guerrieri, Sahand Kashani

Due to increased embedded processing requirements, modern SoCs are becoming heterogeneous computing platforms by combining traditional processing units with custom reconfigurable hardware accelerators (HAs) on an FPGA fabric. However, efficiently managing ...

2019

IMPACT: Interval-based Multi-pass Proteomic Alignment with Constant Traceback

James Richard Larus, Sahand Kashani, Stuart Anthony Byma

Darwin is a genomics co-processor that achieved a 15000x acceleration on long read assembly through innovative hardware and algorithm co-design. Darwins algorithms and hardware implementation were specifically designed for DNA analysis pipelines. This pape ...

2019

A Dynamically Reconfigurable Platform for High-Performance and Low-Power On-Board Processing

Paolo Ienne, Andrea Guerrieri, Sahand Kashani

FPGAs (Field Programmable Gate Array) are an attractive technology for high-speed data processing in space missions due to their unbeatable flexibility and best performance-to-power ratio in comparison to software. However FPGAs suffer from 3 major drawbac ...

IEEE2018