Publications by Grace Zgheib | EPFL Graph Search

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Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Paolo Ienne, Grace Zgheib, Stefan Nikolic

Technology scaling makes metal delay ever more problematic, but routing between Look-Up Tables (LUTs) still passes through a series of transistors. It seems wise to avoid the corresponding delay whenever possible. Direct connections between LUTs, both with ...

ASSOC COMPUTING MACHINERY2020

Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths

Paolo Ienne, Grace Zgheib, Stefan Nikolic

The idea of introducing dedicated, fast paths between certain FPGA elements in order to reduce delay is neither new nor particularly hard to come up with. What is less obvious, however, is how to put such paths to actual use. In this work, we propose an ef ...

IEEE2020

Finding a Needle in the Haystack of Hardened Interconnect Patterns

Paolo Ienne, Grace Zgheib, Stefan Nikolic

Circuits naturally exhibit recurring patterns of local interconnect. Hardening those patterns when designing Field Programmable Gate Array (FPGA) clusters can both eliminate slow programmable connections from the critical path and remove the need for trans ...

IEEE2019

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains

Giovanni De Micheli, Paolo Ienne, Mathias Soeken, Grace Zgheib, Pierre-Emmanuel Julien Marc Gaillardon, Luca Gaetano Amarù, Xifan Tang, Ana Petkovska, Zhufei Chu

Hard-wired carry chains in FPGAs are designed to improve efficiency of important arithmetic primitives. Although they are proven to be effective for arithmetic-rich functions, there are very few studies on the optimization opportunities of carry chains for ...

ACM2017

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element

Paolo Ienne, Grace Zgheib, Yu Lin, Wei Li

The And-Inverter Cone has been introduced as an alternative logic element to the look-up table in FPGAs, since it improves their performance and resource utilization. However, further analysis of the AIC design showed that it suffers from the delay discrep ...

ACM2017

Improved carry chain mapping for the VTR flow

Paolo Ienne, Grace Zgheib, David Novo Bruna, Ana Petkovska

Carry chains facilitate the implementation of adders and improve the performance of arithmetic circuits in FPGAs. The last version of the commonly used open-source Verilog-to-Routing (VTR) CAD flow now enables modelling carry chains in FPGA architectures. ...

IEEE2015

Reducing the Pressure on Routing Resources of FPGAs with Generic Logic Chains

Paolo Ienne, Grace Zgheib, Philip Brisk, Hadi Parandeh Afshar

Routing resources in modern FPGAs use 50% of the silicon real estate and are significant contributors to critical path delay and power consumption; the situation gets worse with each successive process generation, as transistors scale more effectively than ...

Acm Order Department, P O Box 64145, Baltimore, Md 21264 Usa2011

Grace Zgheib

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Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths

Finding a Needle in the Haystack of Hardened Interconnect Patterns

Leading the Blind

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element

Improved carry chain mapping for the VTR flow

Reducing the Pressure on Routing Resources of FPGAs with Generic Logic Chains

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element

Improved carry chain mapping for the VTR flow

Leading the Blind

Finding a Needle in the Haystack of Hardened Interconnect Patterns

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths

Reducing the Pressure on Routing Resources of FPGAs with Generic Logic Chains

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains