Publications by Grace Zgheib | EPFL Graph Search

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Grace Zgheib

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Detailed Placement for Dedicated LUT-Level FPGA Interconnect

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing

Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths

Finding a Needle in the Haystack of Hardened Interconnect Patterns

Leading the Blind

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element

Improved carry chain mapping for the VTR flow

Non-LUT field-programmable gate arrays

Reducing the Pressure on Routing Resources of FPGAs with Generic Logic Chains