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Odysseas Zografos

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Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic

Majority Logic Synthesis

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies

Wave Pipelining for Majority-based Beyond-CMOS Technologies

Exact Synthesis for Logic Synthesis Applications with Complex Constraints

Inversion optimization in majority-inverter graphs

Design and Benchmarking of Hybrid CMOS-Spin Wave Device Circuits Compared to 10nm CMOS

Spintronic Majority Gates

System-level Assessment and Area Evaluation of Spin Wave Logic Circuits

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic

Exact Synthesis for Logic Synthesis Applications with Complex Constraints

Wave Pipelining for Majority-based Beyond-CMOS Technologies

Design and Benchmarking of Hybrid CMOS-Spin Wave Device Circuits Compared to 10nm CMOS

System-level Assessment and Area Evaluation of Spin Wave Logic Circuits

Majority Logic Synthesis

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies

Inversion optimization in majority-inverter graphs

Spintronic Majority Gates