Person

Boris Robert Grot

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Related publications (29)

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Spatial Locality Speculation to Reduce Energy in Chip-Multiprocessor Networks-on-Chip

Boris Robert Grot

As processor chips become increasingly parallel, an efficient communication substrate is critical for meeting performance and energy targets. In this work, we target the root cause of network energy consumption through techniques that reduce link and route ...

Institute of Electrical and Electronics Engineers2014

Network-on-chip using request and reply trees for low-latency processor-memory communication

Babak Falsafi, Boris Robert Grot

A Network-On-Chip (NOC) organization comprises a die having a cache area and a core area, a plurality of core tiles arranged in the core area in a plurality of subsets, at least one cache memory bank arranged in the cache area, whereby the at least one cac ...

2014

Meet the Walkers: Accelerating Index Traversals for In-Memory Databases

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber, Javier Picorel Obando, Kevin Lim

The explosive growth in digital data and its growing role in real-time decision support motivate the design of high-performance database management systems (DBMSs). Meanwhile, slowdown in supply voltage scaling has stymied improvements in core performance ...

2013

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Scale-out datacenters mandate high per-server throughput to get the maximum benefit from the large TCO investment. Emerging applications (e.g., data serving and web search) that run in these datacenters operate on vast datasets that are not accommodated by ...

Ieee2012

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Scale-out server workloads benefit from many-core processor organizations that enable high throughput thanks to abundant request-level parallelism. A key characteristic of these workloads is the large instruction footprint that exceeds the capacity of priv ...

2012

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Manycore chips are emerging as the architecture of choice to provide power efficiency and improve performance, while riding Moore’s Law. In these architectures, on-chip interconnects play a pivotal role in ensuring power and performance scalability. As sup ...

2012

Optimizing Data-Center TCO with Scale-Out Processors

Babak Falsafi, Boris Robert Grot, Pejman Lotfi Kamran

Performance and total cost of ownership (TCO) are key optimization metrics in large-scale data centers. According to these metrics, data centers designed with conventional server processors are inefficient. Recently introduced processors based on low-power ...

Institute of Electrical and Electronics Engineers2012

BugSifter: A Generalized Accelerator for Flexible Instruction-Grain Monitoring

Babak Falsafi, Boris Robert Grot, Yusuf Onur Koçberber, Sotiria Fytraki, Evangelos Vlachos, Jennifer Bedke Sartor

Software robustness is an ever-challenging problem in the face of today's evolving software and hardware that has undergone recent shifts. Instruction-grain monitoring is a powerful approach for improved software robustness that affords comprehensive runti ...

2012

A Qos-Enabled On-Die Interconnect Fabric For Kilo-Node Chips

Boris Robert Grot

To meet rapidly growing performance demands and energy constraints, future chips will likely feature thousands of on-die resources. Existing network-on-chip solutions weren't designed for scalability and will be unable to meet future interconnect demands. ...

2012