Publications by James Richard Larus

Parendi: Thousand-Way Parallel RTL Simulation

James Richard Larus, Thomas Emile Bourgeat

Hardware development critically depends on cycle-accurate RTL simulation. However, as chip complexity increases, conventional single-threaded simulation becomes impractical due to stagnant single-core performance. Parendi is an RTL simulator that addresses ...

ACM2025

A 475 MHz Manycore FPGA Accelerator for RTL Simulation

James Richard Larus, Sahand Kashani

This paper presents the implementation of Manticore: a manycore accelerator for parallel RTL simulation. Manticore packs up to 225 custom soft processors running at 475 MHz on a large FPGA. Implementing manycore accelerators on FPGAs is challenging as desi ...

Association for Computing Machinery, Inc2024

Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism

James Richard Larus, Sahand Kashani

The demise of Moore's Law and Dennard Scaling has revived interest in specialized computer architectures and accelerators. Verification and testing of this hardware depend heavily upon cycle-accurate simulation of register-transfer-level (RTL) designs. The ...

Assoc Computing Machinery2023

Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats

James Richard Larus, Sahand Kashani

As the usage of FPGAs spreads, engineers will inevitably employ them in ways unforeseen-or unwanted-by their manufacturers. Xilinx's toolchains offer multiple points for customizing the FPGA compilation flow, but all flows must end with Vivado as it is the ...

IEEE COMPUTER SOC2022

Auto-Partitioning Heterogeneous Task-Parallel Programs with StreamBlocks

James Richard Larus

FPGAs play an increasing role in the reconfigurable accelerator landscape. A key challenge in designing FPGA-based systems is partitioning computation between processor cores and FPGAs. An appropriate division of labor is difficult to predict in advance an ...

ASSOC COMPUTING MACHINERY2022

Deploying Decentralized, Privacy-Preserving Proximity Tracing

Jean-Pierre Hubaux, James Richard Larus, Marcel Salathé, Mathias Josef Payer, Edouard Bugnion, Carmela González Troncoso, Theresa Stadler, Apostolos Pyrgelis, Sylvain Chatel, Wouter Lueks

2022

Watermarking-based Defense against Adversarial Attacks on Deep Neural Networks

James Richard Larus, Xiaoting Li, Dinghao Wu, Junjun Zhang

The vulnerability of deep neural networks to adversarial attacks has posed significant threats to real-world applications, especially security-critical ones. Given a well-trained model, slight modifications to the input samples can cause drastic changes in ...

IEEE2021

Whose Smartphone Is It?

James Richard Larus

Should two private companies have complete control over the world's cellphones? ...

2021

Enclosure: Language-Based Restriction of Untrusted Libraries

James Richard Larus, Mathias Josef Payer, Edouard Bugnion, Evangelos Marios Kogias, Adrien Ghosn

Programming languages and systems have failed to address the security implications of the increasingly frequent use of public libraries to construct modern software. Most languages provide tools and online repositories to publish, import, and use libraries ...

ACM2021

Abacus: A Tool for Precise Side-channel Analysis

James Richard Larus

Side-channel vulnerabilities can leak sensitive information unconsciously. In this paper, we introduce the usage of Abacus. Abacus is a tool that can analyze secret-dependent control-flow and secret-dependent data-access leakages in binary programs. Unlike ...

IEEE COMPUTER SOC2021