Person
Firat Çelik
This person is no longer with EPFL
Related publications (9)
Energy-Efficient Design Techniques for High-Speed Wireline Serial Links
The exponential growth in computing power and multimedia services has caused a tremendous increase in data traffic in recent years. This increase in data traffic brings a strong demand for data bandwidth of electrical input/output (I/O) links and pushes th ...
EPFL2021A 32 Gb/s PAM-16 TX and ADC-Based RX AFE with 2-tap embedded analog FFE in 28 nm FDSOI
Yusuf Leblebici, Firat Çelik, Ayça Akkaya
This paper presents a 32 Gb/s 16-level pulse amplitude modulation (PAM-16) source-series-terminated transmitter (TX) and a receiver (RX) analog front-end (AFE) in 28 nm FDSOI. The 8-way time-interleaved successive-approximation register (SAR) analog-to-dig ...
2021Analog Neural Networks with Deep-submicron Nonlinear Synapses
Pascal Frossard, Babak Falsafi, Ahmet Caner Yüzügüler, Mario Paulo Drumond Lages De Oliveira, Firat Çelik
Deep neural network (DNN) inference tasks are computationally expensive. Digital DNN accelerators offer better density and energy efficiency than general-purpose processors but still not sufficient to be deployable on resource-constrained settings. Analog ...
2019Analog Neural Networks with Deep-submicron Nonlinear Synapses
Pascal Frossard, Babak Falsafi, Ahmet Caner Yüzügüler, Mario Paulo Drumond Lages De Oliveira, Firat Çelik
Deep neural network (DNN) inference tasks are computationally expensive. Digital DNN accelerators offer better density and energy efficiency than general-purpose processors but still not sufficient to be deployable on resource-constrained settings.Analog c ...
2019JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS
Andreas Peter Burg, Seyed Armin Tajalli, Yusuf Leblebici, Firat Çelik, Ayça Akkaya
JESD204B compliant low-voltage differential signaling (LVDS), and source-series-terminated (SST) transmitters in 28 nm FD-SOI CMOS technology are presented with 1.1 pJ/bit and 1.7 pJ/bit at 12.5 Gb/s, respectively. An external 6.25 GHz single-ended clock, ...
IEEE2019