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This paper presents a 32 Gb/s 16-level pulse amplitude modulation (PAM-16) source-series-terminated transmitter (TX) and a receiver (RX) analog front-end (AFE) in 28 nm FDSOI. The 8-way time-interleaved successive-approximation register (SAR) analog-to-digital-converter (ADC) in the RX AFE has an embedded 2-tap analog feed-forward equalizer. The design objective is to optimize the energy efficiency for the target data rate and the moderate-loss channel. For this purpose, the optimum modulation order that has the least ISI sensitivity for the given equalization capability is decided with a modeling study. All the equalization is performed in the analog domain to avoid the circuit complexity and power consumption disadvantages of the digital equalization in the selected high-order modulation. Thanks to the spectral efficiency of PAM-16 and the analog-only equalization, the figure-of-merit is improved significantly. Post-layout simulations show that the TX consumes 26.85 mW while the RX AFE consumes 49.36 mW at 32 Gb/s with PAM-16, which corresponds to 2.38 pJ/bit for the whole system.