Francesco Gramuglia

Biography

Francesco Gramuglia received the MEng degree in Electronics and Electrical Engineering from the Politecnico di Milano in 2016. From 2015 to 2016 he was a trainee in the STORMlab of Vanderbilt University, Nashville, Tennessee, where he worked on the development of robotic endoscope platforms. In 2016 he received the Best Application Prize and Overall Winner at Surgical Robot Challenge during the Hamlyn Symposium on Medical Robotics at Imperial College, London, 2016. Since 2017, he has been pursuing a Ph.D. degree at the EPFL in the Advanced Quantum Architecture laboratory (AQUA) under the advising of Prof. Edoardo Charbon and Claudio Bruschini, PhD. His research is focused on the design of SPAD based CMOS image sensors and system development for use in biomedical applications, e.g. Time-of-flight Positron emission tomography (TOFPET).

Official source

https://people.epfl.ch/francesco.gramuglia

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A 3.3-Gb/s SPAD-Based Quantum Random Number Generator

Edoardo Charbon, Francesco Gramuglia, Pouyan Keshavarzian

Quantum random number generators (QRNGs) are a burgeoning technology used for a variety of applications, including modern security and encryption systems. Typical methods exploit an entropy source combined with an extraction or bit generation circuit in order to produce a random string. In integrated designs, there is often little modeling or analytical description of the entropy source, circuit extraction, and post-processing provided. In this work, we present a single-photon avalanche diode (SPAD)-based QRNG design, which utilizes the quantum random flip-flop (QRFF) method. Extensive modeling of detector and circuit imperfections that result in entropy degradation is performed. A new method to analytically model serial autocorrelations of the proposed bit generation method, which includes detector dead time, is proposed. Then, a Verilog-AMS model is developed in order to validate the analytical model in simulation. A novel transistor implementation of the QRFF circuit is presented, which enables compensation of the degradation in entropy inherent to the finite non-symmetric transitions of the random flip-flop. Finally, a full system containing two independent arrays of the QRFF circuit is manufactured and tested in a 55-nm bipolar-CMOS-DMOS (BCD) technology node, demonstrating bit generation statistics that are commensurate to the developed model. The full chip is able to generate 3.3 Gb/s of data when operated with an external LED. Pixelwise and spatial analysis of bias and correlation is performed. NIST STS (SP 800-22) and SP 800-90B are used to benchmark the generated bit strings.

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC2023

A 7.5-ps, 60% PDP low-noise SPAD fabricated in CMOS technology

Claudio Bruschini, Edoardo Charbon, Francesco Gramuglia, Pouyan Keshavarzian, Ekin Kizilkan, Myung Jae Lee, Ming-Lo Wu

2022

CMOS SPADs for High Radiation Environments

Claudio Bruschini, Edoardo Charbon, Carlo Alberto Fenoglio, Francesco Gramuglia, Pouyan Keshavarzian, Ekin Kizilkan, Kazuhiro Morimoto, Emanuele Ripiccini, Ming-Lo Wu

2022